Semiconductor Gate Electrode Width Control via Wet Etching
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Solution Overview
Problem
Existing methods for manufacturing semiconductor devices, such as hetero-FETs and HEMTs, face challenges in reducing gate electrode width while minimizing damage to the semiconductor surface, as dry etching causes damage and high-performance exposure is required, whereas wet etching struggles with forming fine features.
Innovation Solution
A method involving the formation of multiple layers on a semiconductor substrate, where a patterned mask is used for selective etching, followed by wet etching to reduce the width of the first layer, allowing for the formation of a gate electrode with reduced width and minimized surface damage, and subsequent removal of layers to create an opening for the electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If dry etching is used to form the insulating layer pattern for reducing gate electrode width, then the gate length can be reduced, but plasma damage occurs to the surface of the semiconductor layer
Solution Approach 1:
The patent segments the etching process into two distinct stages: dry etching to form the initial insulating layer pattern, followed by wet etching to reduce the gate electrode width. This segmentation allows each method to be optimized for its specific function - dry etching for pattern formation and wet etching for precise width reduction without plasma damage
Solution Approach 2:
The patent introduces wet etching as an intermediary process between dry etching and gate electrode formation. This intermediary wet etching step removes the insulating layer material precisely without exposing the semiconductor surface to plasma, thereby mediating between the need for width reduction and the need to avoid surface damage
2Object-affected harmful factors
If wet etching is used to form the insulating layer pattern to avoid surface damage, then surface damage is reduced, but fine features cannot be formed
Solution Approach 1:
The patent divides the etching process into two segmented steps with distinct functions: dry etching performs the initial pattern formation with high precision for fine features, while wet etching subsequently reduces the width with high precision while avoiding surface damage. Each segment is optimized for its specific role
Solution Approach 2:
The patent performs preliminary dry etching to establish the insulating layer pattern before performing the subsequent wet etching for width reduction. This preliminary action creates a foundation that guides the second etching step, ensuring both fine feature formation and precise width control
3Manufacturing precision
If a patterned resist is used to define the opening for gate electrode formation, then the gate electrode width matches the resist pattern width, but a high performance exposure apparatus is required
Solution Approach 1:
The patent uses the insulating layer as an intermediary element that decouples the resist pattern width from the final gate electrode width. The insulating layer is formed with a width larger than the desired gate electrode, then precisely removed by wet etching to achieve the target width, eliminating the need for high-precision exposure
Solution Approach 2:
The patent replaces the optical precision requirement of high-performance exposure apparatus with a chemical etching process. Instead of relying on optical systems to define the exact gate width, the process uses wet etching chemistry to precisely remove material to the desired width, substituting optical mechanics with chemical precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the width of the gate electrode while minimizing damage to the semiconductor surface, using a simple and efficient process that can be adjusted for precise control of the gate length, suitable for high-frequency semiconductor devices.
Implementation Method 1
a wet etching step of etching the first layer to a width which is less than the width of the patterned mask, wherein the etch rate of the first layer is higher than that of the second layer
Implementation Method 2
a step of applying an ashing treatment to a portion of the Si oxide exposed through the patterned mask to form an oxygen-rich portion in the Si oxide
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.