Semiconductor Gate Wiring Isolation for Threshold Voltage Stability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor devices, the proximity of gate wiring to the base layer can cause fluctuations in threshold voltage due to potential influence on the channel, leading to unreliable device operation.

Innovation Solution

The semiconductor device design includes a gate electrode groove in contact with a drift region, a well region, and a source region, with gate wiring electrically insulated and formed inside a source electrode groove, reducing the impact of gate wiring on the channel and stabilizing threshold voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If gate wiring is formed on the front surface side of the drift layer near the base layer, then the device structure is simplified and manufacturing is easier, but the potential of the gate wiring influences the channel causing threshold voltage fluctuation

Engineering Contradiction:
Improveease of manufactureVSAvoidthreshold voltage stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate wiring is moved from the front surface (two-dimensional plane near the channel) to the back surface of the drift layer (different spatial dimension), eliminating proximity to the channel while maintaining electrical connectivity through the drift layer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate wiring is embedded within the back surface structure of the drift layer, nesting the wiring within the existing device architecture rather than adding it as a separate external component

Inventive Principle:
Principle #7Nested doll (Nesting)

2Device complexity

If gate wiring is positioned near the base layer for compact design, then device integration is improved, but channel potential fluctuation occurs leading to threshold voltage instability

Engineering Contradiction:
Improvedevice integrationVSAvoidthreshold voltage stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The gate wiring is repositioned to the back surface of the drift layer, utilizing the third dimension (depth) to achieve compact integration while maintaining sufficient distance from the channel to prevent potential fluctuation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces threshold voltage fluctuations, enhances the degree of integration, and improves withstand voltage performance by isolating the gate wiring from the source electrode and channel, leading to more reliable device operation.

Implementation Method 1

a gate electrode formed on a surface of the gate electrode groove via an insulating film

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

a gate wiring electrically insulated from the source electrode and formed inside the source electrode groove in contact with the gate electrode

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS10937874B2Semiconductor device
Publication Date: 2021.03.02 NISSAN MOTOR CO LTD
  • US10937874B2 patent drawing
  • US10937874B2 patent drawing
  • US10937874B2 patent drawing

AI summary

A semiconductor device includes: a gate electrode groove formed in contact with a drift region, a well region, and a source region; a gate electrode formed on a surface of the gate electrode groove via an insulating film; a source electrode groove in contact with the gate electrode groove; a source electrode electrically connected to a source region; and a gate wiring electrically insulated from the source electrode and formed inside the source electrode groove in contact with the gate electrode.