Semiconductor Device Gate Electrode Between Wiring Layers
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Solution Overview
Problem
The miniaturization of semiconductor elements is limited by the resolution limit of lithography in traditional wiring layer structures, restricting the shortening of channel length and hindering performance improvement.
Innovation Solution
A semiconductor device design where a gate electrode is positioned between source/drain electrodes in stacked wiring layers, with a gate insulation film covering its sides, allowing the channel length to be defined by the gate electrode's thickness rather than lithography resolution, enabling independent selection of materials and thickness for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is shortened to improve semiconductor element performance, then the performance improves, but the lithography resolution limit restricts further miniaturization
Solution Approach 1:
The patent transitions from defining channel length in the planar direction (constrained by lithography resolution) to defining it in the vertical direction through gate electrode thickness. By stacking wiring layers and positioning the gate electrode between source/drain electrodes in the thickness direction, the channel length can be controlled by film thickness rather than lithographic patterning, enabling shorter channel lengths that overcome the lithography resolution limit.
2Device complexity
If wires in the same wiring layer are used as source/drain electrodes with gate electrode below, then the structure is simple, but the channel length is restricted by lithography resolution
Solution Approach 1:
The invention moves the channel length definition from the lateral dimension (where lithography resolution limits apply) to the vertical dimension (where film thickness control provides higher precision). By forming the gate electrode in a wiring layer between source/drain electrodes in the thickness direction, the channel length becomes a vertical dimension parameter controlled by deposition thickness rather than lateral patterning.
Solution Approach 2:
The patent separates the gate electrode formation from the source/drain electrode formation by placing them in different wiring layers. This segmentation allows independent optimization of each component and enables the gate electrode thickness to define channel length without being constrained by the lithography processes used for wire patterning.
Data Source
AI summary
The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.