Semiconductor Module Gate Wiring Layout for Equalized Switching
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Solution Overview
Problem
Conventional semiconductor modules experience variations in switching speed and increased switching loss due to differences in wiring lengths between semiconductor chips and their respective terminals, leading to potential chip breakdown and inefficiencies.
Innovation Solution
The semiconductor module incorporates first and second adjusting gate and sense wirings, which are embedded in the resin case, to equalize wiring lengths and reduce inductance, thereby minimizing current concentration and preventing chip breakdown while allowing for miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wiring connections are used between semiconductor chips and terminals, then the module structure is simple, but wiring length differences cause switching speed variations and increased switching loss
Solution Approach 1:
The wiring structure is segmented into multiple independent wiring patterns on the insulating substrate, each specifically designed to connect to particular semiconductor chips. This segmentation allows precise control of wiring lengths for each chip connection, reducing switching loss by equalizing inductance values across parallel-connected chips.
Solution Approach 2:
Different wiring patterns are designed with different local characteristics to match the specific requirements of different semiconductor chip positions. The wiring lengths and routes are locally optimized for each chip group, ensuring that chips at different locations experience comparable switching conditions and inductance values.
2Reliability
If wiring lengths between semiconductor chips and terminals are not equalized, then the wiring structure is simple, but switching speed variations occur leading to current concentration and chip breakdown
Solution Approach 1:
The wiring design achieves equipotentiality in terms of electrical inductance by carefully controlling wiring lengths and routes. All semiconductor chips connected in parallel experience comparable inductance values through the insulating substrate wiring patterns, preventing voltage variations and current concentration that would lead to chip breakdown.
Solution Approach 2:
The wiring length equalization is built into the insulating substrate design from the beginning, before chip mounting. The wiring patterns are pre-configured with optimized lengths and routes to ensure that when chips are mounted, they automatically receive equalized electrical characteristics without requiring additional adjustment steps.
3Ease of manufacture
If traditional wiring methods are used, then manufacturing is simple, but switching loss increases due to wiring length differences
Solution Approach 1:
The wiring patterns are merged into the insulating substrate itself, combining the substrate function with the wiring function. This integration allows multiple wiring patterns with different length characteristics to be manufactured simultaneously in a single substrate fabrication process, maintaining manufacturing simplicity while achieving the complex wiring length equalization needed to reduce switching loss.
Data Source
AI summary
A semiconductor module including: a plurality of first semiconductor chips; a resin case provided surrounding an accommodation space for accommodating the plurality of first semiconductor chips; a first gate terminal connected to a gate pad of the plurality of first semiconductor chips; a plurality of first main gate wirings provided in the accommodation space, each of which is connected to the gate pad of the plurality of first semiconductor chips; and a first adjusting gate wiring arranged between at least one of the plurality of first main gate wirings and the first gate terminal, and configured to adjust a difference in wiring lengths between the plurality of first semiconductor chips and the first gate terminal is provided.