Semiconductor Gate Structure Work Function Modulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in forming semiconductor devices with metal electrodes on insulating films made of materials with a higher dielectric constant than SiO2, while achieving desired work functions, as conventional techniques face difficulties in controlling threshold voltages and maintaining high-k material compatibility, especially with the FUSI/high-k interface causing work function modulation issues.
Innovation Solution
The solution involves forming semiconductor devices with gate insulating films containing silicon, oxygen, and nitrogen, and interfacial layers with specific metallic bond distributions, specifically using a 13-group element like boron and a 15-group element like phosphorus, segregated at the interface between the gate electrode and insulating films, to modulate work functions effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a high-k material is used as the gate insulating film to reduce leakage current, then power consumption is reduced, but the work function modulation by impurities is lost and threshold voltage control becomes difficult
Solution Approach 1:
A silicide layer is introduced as an intermediary between the high-k gate insulating film and the gate electrode. This silicide layer serves as a mediator that enables work function modulation through impurity segregation, thereby restoring threshold voltage control capability while maintaining the low leakage current benefits of the high-k material.
Solution Approach 2:
The gate structure employs a composite configuration consisting of multiple layers: high-k gate insulating film, silicide layer, and gate electrode. This composite structure combines the advantages of high-k material (low leakage) with the work function modulation capability of silicide, achieving both reduced power consumption and precise threshold voltage control.
2Reliability
If the FUSI technique is used to form metal gate electrodes, then problems such as gate parasitic resistance and impurity spread are solved, but the device manufacturing process becomes complicated
Solution Approach 1:
The formation of the silicide layer is merged with the existing gate electrode formation process. The silicide layer is deposited and processed together with the gate electrode materials, combining multiple functions into a single integrated structure, thereby reducing process complexity while maintaining the benefits of metal gate electrodes.
3Loss of energy
If the gate insulating film thickness is increased to reduce leakage current, then power consumption is reduced, but the device area and capacitance are affected
Solution Approach 1:
The dielectric constant (k-value) of the gate insulating film is changed from conventional values to high-k values. This parameter change allows achieving the same leakage current reduction with a thinner physical film thickness, thereby maintaining device area and capacitance characteristics while reducing power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the achievement of desired work functions in both p-channel and n-channel transistors, optimizing threshold voltages and reducing leakage currents, thereby enhancing the performance of CMOS logic devices and memory cells without increasing insulating film thickness or complicating the manufacturing process.
Implementation Method 1
segregated at the interface between the gate electrode and insulating films
Implementation Method 2
converting the silicon layer into a metal silicide layer by chemically reacting the silicon layer and the metal layer
Implementation Method 3
by diffusing the 13-group element and the 15-group element through a heat treatment
Data Source
AI summary
A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and containing a 13-group element. The total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer.