Semiconductor Global Column Redundancy Test Circuit
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Solution Overview
Problem
The global column redundancy method for semiconductor devices is complex due to the need for identifying which bit line to replace among multiple defective bit lines, necessitating a simplification of the test process to enhance recovery efficiency.
Innovation Solution
A test circuit is implemented that includes a data generating circuit and an analyzing circuit to generate an expected value based on majority voting of read data-bits, allowing for the identification of defective bit lines without requiring a circuit to hold expected values, thereby simplifying the detection process and enabling efficient replacement using a spare column plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the global column redundancy method is used to replace defective bit lines with bit lines in a spare column plane, then the recovery efficiency is improved, but the test process becomes complicated requiring identification of which specific bit line to replace
Solution Approach 1:
The semiconductor device performs self-diagnosis by automatically detecting which bit line is defective through majority voting of read data bits. The device generates expected values from read data, compares them with actual read data, and identifies defective bit lines without external intervention, thereby simplifying the test process while maintaining high recovery efficiency
Solution Approach 2:
The system implements feedback by comparing read data with expected values generated through majority voting. When mismatches are detected, the system uses the mismatch information to identify defective bit lines and automatically configure replacement, creating a closed-loop test process that reduces complexity
2Measurement precision
If a circuit to hold expected values is implemented to identify defective bit lines, then the detection accuracy is improved, but the circuit scale increases
Solution Approach 1:
Instead of holding complete expected values in separate storage circuits, the system generates expected values by copying and processing actual read data through majority voting logic. This approach maintains detection accuracy while avoiding the need for additional expected value storage circuits
Solution Approach 2:
The functions of reading data, generating expected values, and detecting defective bit lines are merged into a single integrated process. The expected values are generated on-the-fly from read data using majority voting, combining multiple functions into one circuit block and reducing overall circuit scale
Data Source
AI summary
Disclosed herein is an apparatus that includes a plurality of column planes each including a plurality of bit lines, an access control circuit configured to select one of the plurality of bit lines in each of the plurality of column planes based on a column address to read a plurality of data-bits, a data generating circuit configured to generate an expected-bit based at least in part on the data-bits, and an analyzing circuit configured to generate a fail-bit data indicating which one of the data-bits does not match the expected-bit when one of the data-bits does not match the expected-bit.