Semiconductor Chip Post-Passivation Gold Bump Redistribution
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Solution Overview
Problem
The increasing number of I/Os in semiconductor chips requires smaller Au bumps, making it difficult to connect the chip to external circuitry without damaging underlying semiconductor devices due to shock, and conventional designs limit the placement of semiconductor devices near the chip edge.
Innovation Solution
The implementation of soft and ductile metal bumps over a redistribution layer (RDL) that changes the I/O layout from fine-pitched to coarse-pitched contact pads, allowing semiconductor devices to be placed under the metal bumps and near the chip edge, thereby absorbing shock and facilitating easier metal bump formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/Os is increased, then the functionality of the chip is improved, but the size of Au bumps must be shrunk making connection to external circuitry difficult and expensive
Solution Approach 1:
A redistribution layer (RDL) is introduced as an intermediary between the fine-pitched contact pads and the metal bumps. The RDL redistributes the I/O signals and provides a coarser pitch for metal bump formation, making the connection process easier and less expensive while maintaining high I/O functionality
Solution Approach 2:
The patent transitions from a two-dimensional layout where contact pads are directly exposed at the chip periphery to a three-dimensional structure with RDL layers. This allows fine-pitched contact pads to be connected to coarser-pitched metal bumps through vertical interconnections, solving the manufacturing difficulty
2Area of stationary object
If Au bumps are shrunk to maintain small chip size, then the chip size is reduced, but it becomes technically difficult and economically expensive to connect the chip to external circuitry
Solution Approach 1:
By introducing RDL layers, the patent creates a vertical dimension for signal redistribution. This allows the chip to maintain small size while using larger, easier-to-manufacture metal bumps for external connections through the RDL intermediary structure
Solution Approach 2:
The RDL acts as a mediator that decouples the size constraint from the connection difficulty. Small fine-pitched contact pads can coexist with larger coarser-pitched metal bumps through the RDL, enabling easy external connection without increasing chip size
3Adaptability or versatility
If contact pads are aligned in two rows to increase I/O, then the number of I/Os is increased, but the chip cannot be maintained in a small size since the peripheral region vacates no semiconductor devices
Solution Approach 1:
The patent uses vertical RDL layers to redistribute I/O signals, allowing contact pads to be arranged in compact patterns rather than requiring extended peripheral rows. This enables high I/O count while maintaining small chip footprint
Solution Approach 2:
The I/O functionality is segmented across multiple RDL layers, allowing contact pads to be distributed throughout the chip area rather than concentrated at the periphery. This enables efficient space utilization and small chip size with high I/O count
4Reliability
If metal bumps are made soft and ductile to absorb shock energy, then the reliability is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent changes the material parameters of metal bumps to be soft and ductile, enabling shock energy absorption. This material parameter change improves reliability without significantly complicating the manufacturing process, as the RDL structure already provides a robust connection framework
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows semiconductor devices to be placed under the metal bumps without damage from shock, enables easier metal bump formation, and allows for a more compact semiconductor chip design by optimizing the use of the chip's surface area.
Implementation Method 1
The Au bumps are soft and ductile to buffer and absorb the shock energy during assembling the semiconductor chip and an external circuitry or to buffer and absorb the shock energy during a probe or testing card is poked in the metal bumps
Data Source
AI summary
The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.