Semiconductor Device With Graded Anode Impurity Profile
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Solution Overview
Problem
Current power semiconductor devices, such as diodes and IGBTs, face challenges in improving ON voltage, switching speed, reverse-biased safety operation, and current vibration, particularly in power converting devices like inverters, where existing designs struggle to balance impurity concentration and carrier discharge effectively.
Innovation Solution
The semiconductor device incorporates a vertical p-intrinsic-n (pin) diode structure with specific impurity concentration profiles and buried bodies to manage hole injection and carrier discharge, including an n-type semiconductor layer between the p-type anode and anode electrode, and trench structures with buried electrodes to enhance switching speed and suppress parasitic transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If impurity concentration in the anode layer is increased to reduce ON voltage, then conduction loss is reduced, but switching speed deteriorates and current vibration increases
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the anode layer. The anode layer has a first impurity concentration in its first region (closer to the base layer) and a second impurity concentration in its second region (closer to the semiconductor layer), where the first concentration is higher than the second. This gradient structure allows the lower-concentration region to facilitate fast carrier discharge for quick switching, while the higher-concentration region provides good conduction properties, thus resolving the contradiction between switching speed and conduction loss.
2Loss of energy
If impurity concentration in the anode layer is increased to improve conduction, then ON voltage is reduced, but current vibration upon turnoff increases
Solution Approach 1:
The patent uses local quality by establishing different impurity concentrations in different regions of the anode layer. The first region has a higher impurity concentration to support low ON voltage and good conduction, while the second region has a lower impurity concentration to enable controlled carrier discharge that suppresses current vibration during turnoff. This spatial differentiation of impurity concentration allows simultaneous optimization of conduction performance and switching behavior.
3Speed
If carrier discharge speed is increased to improve switching speed, then turnoff time is reduced, but current vibration increases
Solution Approach 1:
The patent applies parameter changes by varying the impurity concentration parameter across the anode layer. The impurity concentration is changed from a first value in the first region to a second value in the second region, creating a gradient that controls the carrier discharge rate. This gradual parameter change allows carriers to be discharged at a controlled pace, achieving fast switching without the abrupt carrier removal that causes current vibration.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.