Semiconductor Grid Array Package with Conductive Runners
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Solution Overview
Problem
Conventional lead frame based grid array packages face issues such as soldering shorts, loose external electrical connections, and resin bleed, which limit their reliability and increase costs compared to substrate-based packages, while also being restricted by the number of external connections due to package size constraints.
Innovation Solution
A semiconductor die grid array package is developed using a housing member with a cavity and electrically conductive runners, where bond wires are selectively bonded to external connection pads and connected to the runners, and external connectors are mounted, allowing for increased connectivity without size increase, and addressing the issues of resin bleed and connection reliability through a method involving molding, sputter coating, and plating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lead frame based grid array package is used, then the number of external electrical connections is increased, but soldering shorts occur between adjacent external electrical connections
Solution Approach 1:
The patent introduces a mold compound as an intermediary material that fills the spaces between external electrical connections and provides physical separation. This mediator prevents direct contact between adjacent connections during soldering, eliminating the short circuit risk while maintaining high connection density.
Solution Approach 2:
The patent uses a thin film-like mold compound that conformally coats and isolates the external electrical connections. This flexible encapsulating layer provides sufficient separation between adjacent connections without adding significant height or volume to the package.
2Ease of manufacture
If thin sheet of conductive material is used for external electrical connections, then manufacturing is simplified, but connections become loose and are not sufficiently held within mold compound
Solution Approach 1:
The patent merges the external electrical connections with the mold compound by embedding the conductive sheets within the encapsulating material. This combination ensures that the connections are mechanically supported and held firmly in position, preventing loosening while maintaining the simplicity of using thin conductive sheets.
Solution Approach 2:
The patent creates a composite structure where thin conductive sheets are integrated within the mold compound matrix. This composite approach provides both the manufacturing simplicity of thin sheets and the mechanical stability of being embedded in a supporting material, preventing connection loosening.
3Reliability
If molding process is used to encapsulate die and leads, then protection is provided, but resin bleed occurs affecting yield and reliability
Solution Approach 1:
The patent modifies the molding process parameters, specifically controlling the molding temperature and pressure conditions to prevent resin bleed. By optimizing these parameters, the mold compound encapsulates the die and leads effectively without excessive flow that would cause bleeding, thereby maintaining both protection and manufacturing yield.
4Ease of operation
If QFP structure is used, then ease of connection to circuit board is achieved, but the number of leads is limited for specific package size
Solution Approach 1:
The patent transitions from the planar lead arrangement of QFP to a three-dimensional grid array configuration. By stacking connections in multiple layers and dimensions, the package achieves both the ease of board connection and a significantly increased number of external electrical connections within the same package footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a cost-effective semiconductor die grid array package with improved yield and reliability by increasing the number of external connections without size increase, reducing the risk of resin bleed, and ensuring stable electrical connections.
Implementation Method 1
bond wires are selectively bonded to the external connection pads
Implementation Method 2
the semiconductor die and leads are encapsulated in a compound (material) such as a plastic material
Implementation Method 3
a method involving molding, sputter coating, and plating processes
Implementation Method 4
a method involving molding, sputter coating, and plating processes
Data Source
AI summary
A semiconductor grid array package has a first housing member with a cavity that has a cavity floor and cavity walls. A semiconductor die is affixed to the cavity floor. A second housing member is molded to the first housing member and covers an interface surface of the die. Electrically conductive runners are mounted to an external surface of the second housing member. The runners have a wire contacting area and an external connector contacting area. Bond wires are selectively bonded to the external connection pads of the semiconductor die and selectively connected to the wire contacting area of the runners. External electrical connectors are mounted to a designated external connector contacting area.