Semiconductor encapsulation groove design for adhesive containment
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Solution Overview
Problem
Existing semiconductor encapsulation methods face contamination issues due to overflowing bonding adhesive, which reduces the utilization rate of chip sizes and requires increased spacing between chip mounting areas, limiting the compactness and efficiency of semiconductor packaging.
Innovation Solution
A metal clip semiconductor encapsulation structure and method that includes a lead frame with grooves on the chip carrier to contain and direct the bonding adhesive, allowing for closer chip placement and reduced contamination, featuring a groove design that isolates chip mounting areas and pins, and a process that involves using metal clips to connect chips and pins while encapsulating with a plastic package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If bonding adhesive is applied to mount chips on chip carrier, then chips are securely attached to chip carrier, but bonding adhesive overflows and contaminates chip mounting equipment
Solution Approach 1:
The chip carrier is divided into multiple isolated chip mounting areas by grooves. Each mounting area is separated from others, preventing adhesive overflow from one area to contaminate other areas or the mounting equipment. The grooves act as physical barriers that segment the adhesive containment zones.
Solution Approach 2:
The grooves serve as intermediary structures between chip mounting areas and the surrounding environment. They intercept and contain the overflowing bonding adhesive, preventing direct contact between the adhesive and chip mounting equipment. The grooves mediate the adhesive flow path to a safe containment zone.
2Object-affected harmful factors
If spacing between chip mounting areas is increased to prevent adhesive overflow, then contamination is reduced, but chip size utilization rate decreases
Solution Approach 1:
Instead of increasing horizontal spacing between chip mounting areas (2D approach), the solution introduces a vertical dimension with grooves that have depth. The grooves extend downward to contain adhesive overflow, allowing chip mounting areas to be placed closer together horizontally while still preventing contamination. This dimensional transition maximizes chip area utilization.
3Adaptability or versatility
If chip carrier and pins are disconnected with gap to allow adhesive flow, then chip mounting is flexible, but adhesive drips onto mounting equipment
Solution Approach 1:
The harmful function of the gap (allowing adhesive to drip onto equipment) is extracted and replaced. Instead of relying on the gap between chip carrier and pins to accommodate adhesive, the grooves are introduced on the chip carrier surface to specifically contain the adhesive. This separates the mounting flexibility function from the adhesive containment function.
4Adaptability or versatility
If multiple chips are co-packaged with disconnected mounting areas, then chip variety is increased, but adhesive overflow contaminates equipment
Solution Approach 1:
The chip carrier is segmented into multiple independent chip mounting areas by grooves. Each area can accommodate different chip types while being physically isolated from others. The grooves prevent adhesive from one chip mounting area from flowing to and contaminating other areas or the mounting equipment, enabling versatile multi-chip packaging.
Data Source
AI summary
A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.