Semiconductor Etching Openings With Tuned Groove Diameters for LCDU

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Solution Overview

Problem

The continuous reduction in feature dimensions of semiconductor structures, particularly in DRAMs, leads to excessive low local CD uniformity (LCDU), affecting electrical performance due to inconsistent mask hole sizes and potential laps between semiconductor structures.

Innovation Solution

A method involving the formation of grooves with differing inner diameters in a dielectric layer, followed by an initial filling layer deposition with controlled thickness and ion implantation, and subsequent etching to create etching openings with precise diameter differences, enhancing uniformity and electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the feature dimension of semiconductor structure is reduced to increase integration density, then the productivity and storage capacity are improved, but the local CD uniformity deteriorates due to inconsistent mask hole sizes

Engineering Contradiction:
Improveintegration densityVSAvoidlocal CD uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating the inner diameters of grooves into different specifications (first, second, and third specifications) based on their local position requirements. Different groove regions are assigned different diameter tolerances to achieve optimal local CD uniformity while maintaining high integration density overall.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of groove inner diameter by establishing multiple diameter specifications rather than using a uniform diameter. This parameter differentiation allows the mask structure to accommodate variations in etching processes and maintain precision across different locations, resolving the contradiction between high density and uniformity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the mask hole size is reduced to achieve smaller feature dimensions, then the integration density is improved, but the electrical performance deteriorates due to laps between semiconductor structures

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent ensures reliable electrical performance by assigning different inner diameter specifications to grooves based on their functional requirements. Critical grooves that form semiconductor structures have tighter diameter controls to prevent laps, while non-critical grooves have more relaxed specifications, maintaining both high density and electrical reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs preliminary classification and assignment of different groove diameter specifications before the etching process. This preliminary action ensures that grooves requiring precise dimensions for electrical performance are identified and controlled in advance, preventing laps and ensuring reliable electrical connections while maintaining high integration density.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves local CD uniformity and electrical properties by ensuring consistent etching openings, thereby improving the precision and yield of semiconductor structures.

Implementation Method 1

initial filling layer deposition with controlled thickness and ion implantation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12406856B2Method of manufacturing semiconductor structure and semiconductor structure
Publication Date: 2025.09.02 CHANGXIN MEMORY TECH INC
  • US12406856B2 patent drawing
  • US12406856B2 patent drawing
  • US12406856B2 patent drawing

AI summary

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a base; forming a first dielectric layer having grooves, where the grooves include a first groove and a second groove whose inner diameters have a first difference; forming an initial filling layer in the first groove and the second groove, where the first groove forms a third groove, the second groove forms a fourth groove, and an inner diameter of the third groove and that of the fourth groove have a second difference less than the first difference; processing the initial filling layer to form a filling layer; and forming a plurality of etching openings whose inner diameters have a preset difference on a surface of the base.