Semiconductor Package Groove Prevents Encapsulant Bleeding
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Solution Overview
Problem
The manufacturing of fan-out semiconductor packages is hindered by a common defect where the encapsulant bleeds into connection pads, leading to open defects, decreased via connectivity, and electrical short-circuits, which compromises the reliability of the vias.
Innovation Solution
A semiconductor package design that incorporates a groove on the active surface of the semiconductor chip, with a width greater at the internal region than the entrance region, to prevent encapsulant bleeding, and a frame with a through-hole to accommodate the chip and improve encapsulant coverage, enhancing via reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fan-out semiconductor package is manufactured with conventional structures, then the package achieves compact size and pin redistribution, but the encapsulant bleeds into connection pads causing open defects and via connectivity issues
Solution Approach 1:
The groove is formed on the active surface of the semiconductor chip before the encapsulation process. This preliminary structural preparation creates a barrier that prevents the encapsulant from bleeding into the connection pads during the encapsulation process, thereby solving the reliability issue without requiring changes to the encapsulation process itself.
Solution Approach 2:
The groove acts as an intermediary barrier between the encapsulant and the connection pads. By introducing this intermediate structure, the direct harmful interaction between the encapsulant and the connection pads is prevented, thereby maintaining via connectivity and preventing open defects.
2Ease of manufacture
If the groove width is uniform throughout, then the manufacturing process is simpler, but the encapsulant can still penetrate into the connection pad region
Solution Approach 1:
The groove is designed with asymmetric width characteristics - wider at the bottom and narrower at the top opening. This asymmetric geometry creates a mechanical barrier that effectively contains the encapsulant while preventing it from reaching the connection pads. The wider bottom portion provides better containment, while the narrower opening maintains ease of fabrication.
Solution Approach 2:
The groove width is varied locally along its depth - wider at the bottom region and narrower at the top opening. This local variation in geometry provides enhanced encapsulant containment at the critical bottom region while maintaining manufacturability at the accessible top opening, thereby resolving the contradiction between ease of manufacture and reliability.
3Reliability
If the encapsulant coverage is increased to improve board-level reliability, then the package becomes more robust, but the encapsulant bleeding defect persists
Solution Approach 1:
The groove structure is prepared in advance on the semiconductor chip before encapsulation. This preliminary action creates a preventive barrier that allows the encapsulant to be applied with extended coverage for board-level reliability without causing bleeding defects, as the groove contains the encapsulant away from the connection pads.
Solution Approach 2:
The groove serves as an intermediary barrier that enables the encapsulant to provide enhanced coverage and protection while preventing it from directly contacting the connection pads. This intermediary structure allows the package to achieve both robust encapsulant coverage and freedom from bleeding defects.
Data Source
AI summary
A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and having the active surface disposed on the connection structure to face the connection structure, and an encapsulant covering at least a portion of the semiconductor chip, wherein the semiconductor chip includes a groove formed in the active surface, and the groove has a shape in which a width of a region of at least a portion of an internal region located closer to a central portion of the semiconductor chip than the active surface is greater than a width of an entrance region.