Semiconductor Groove Etching for High Density Chip Yield
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Solution Overview
Problem
Current methods for producing semiconductor pieces from a substrate, such as those with light-emitting elements, face challenges in maximizing the number of pieces obtained due to limitations in etching techniques, leading to inefficiencies in chip size reduction and increased plane occupancy area during mounting, which hinders cost reduction and device thickness minimization.
Innovation Solution
A method involving anisotropic dry etching to form front-surface-side grooves with a narrow width and deep depth, followed by changing etching conditions to create a wider second groove portion, allowing for effective thinning of the substrate and reducing chip size while minimizing adhesive residue and chip cracking, thereby increasing the density of semiconductor pieces and reducing the plane occupancy area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching techniques are used to form grooves for dividing substrates, then the substrate can be divided into semiconductor pieces, but the number of pieces obtained per substrate is limited and chip size cannot be sufficiently reduced
Solution Approach 1:
The patent applies parameter changes by modifying etching conditions (gas flow rates, power, pressure) during the etching process to create grooves with specific width variations. The etching conditions are changed mid-process to produce a first groove portion with a first width and a second groove portion with a second width smaller than the first width, enabling more precise control over the final chip dimensions and allowing higher density arrangements.
Solution Approach 2:
The groove formation process is segmented into multiple stages: forming a first groove portion with initial etching conditions, then changing conditions to form a second groove portion with different width characteristics. This segmentation of the etching process allows for optimized chip sizing and higher piece density per substrate.
2Productivity
If narrower grooves are formed to reduce chip size, then more pieces can be obtained per substrate, but adhesive residue and chip cracking increase during the thinning process
Solution Approach 1:
The patent changes etching parameters mid-process to create a groove structure with a wider first groove portion and a narrower second groove portion. This width variation reduces stress concentration during subsequent thinning and adhesive application processes, minimizing chip cracking and adhesive residue while maintaining high piece density.
Solution Approach 2:
The groove structure is designed with a wider first groove portion that acts as a cushioning zone before the narrower second groove portion. This pre-designed width variation compensates for stresses that will occur during thinning and mounting, preventing adhesive residue and cracking before they can occur.
3Ease of manufacture
If uniform width grooves are formed by conventional etching, then the process is simple, but the plane occupancy area during mounting is increased
Solution Approach 1:
The patent modifies etching parameters during the process to create non-uniform groove widths. The first groove portion has a larger width while the second groove portion has a smaller width, optimizing the plane occupancy area during mounting while maintaining manufacturing feasibility through controlled parameter changes.
Solution Approach 2:
The etching process transitions from static (uniform conditions) to dynamic (changing conditions mid-process). The etching parameters are dynamically adjusted to create the two-stage groove structure, enabling optimized space utilization during mounting while keeping the process relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of semiconductor pieces by allowing for a higher density of light-emitting elements on the wafer, reduces chip size, and minimizes the plane occupancy area during mounting, thus achieving cost-effective and efficient semiconductor production.
Implementation Method 1
forming a first groove portion of a front-surface-side groove by anisotropic dry etching from a front surface of a substrate
Data Source
AI summary
A method for producing a semiconductor piece includes forming a first groove portion of a front-surface-side groove by anisotropic dry etching from a front surface of a substrate, forming a second groove portion of the front-surface-side groove, the second groove portion being located below and in communication with the first groove portion and having a width wider than a width of the first groove portion, and thinning the substrate from a back surface of the substrate up to the second groove portion. The second groove portion is formed by changing an etching condition of the anisotropic dry etching during the formation of the front-surface-side groove so that the width of the second groove portion is wider than the width of the first groove portion.