Semiconductor Device Groove Solder Blocking
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Solution Overview
Problem
In semiconductor devices with closely packed semiconductor chips, solder spread and void formation can lead to positional deviations and compromised heat dissipation, as the solder may spread into groove portions on the circuit board, causing contact between chips and creating voids under the chips.
Innovation Solution
A semiconductor device design featuring a ceramic circuit board with groove portions between chip disposition areas, where bonding wires are strategically placed across these grooves to block solder spread and prevent positional deviations, ensuring reliable chip placement and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are disposed in close proximity to improve packaging density, then packaging density is improved, but solder may spread and be pressed out from disposition areas causing positional deviations and chip contact
Solution Approach 1:
The gap between disposition areas is segmented into multiple regions by forming groove portions that divide the gap into a first gap region and a second gap region. This segmentation prevents solder from spreading across the entire gap, thereby maintaining positioning accuracy while allowing close proximity disposal of semiconductor chips.
Solution Approach 2:
The groove portions are formed locally in specific regions of the circuit board between disposition areas, creating localized barriers that affect only the solder flow in those specific areas. This local modification prevents solder spread without affecting the overall chip disposition arrangement or requiring changes to the chip packages themselves.
2Manufacturing precision
If groove portions are formed in circuit board gaps to prevent solder spread, then positioning accuracy is improved, but voids may be included in solder reaching the groove portion
Solution Approach 1:
The groove portions segment the gap into multiple regions and create a controlled pathway for solder flow. The solder is guided to fill the groove portions completely, ensuring that voids are eliminated while the segmented structure prevents excessive solder spread that would cause positioning deviations.
Solution Approach 2:
The groove portions are formed in advance on the circuit board before soldering. This preliminary structuring of the gap region guides the solder flow during the soldering process, ensuring proper filling and preventing both void formation and excessive spread, thereby simultaneously achieving positioning accuracy and reliable heat dissipation.
3Reliability
If solder is allowed to spread freely to fill gaps, then void formation is prevented, but semiconductor chips may come in contact with each other
Solution Approach 1:
The groove portions divide the gap into controlled regions that guide solder flow. This segmentation allows solder to fill the groove portions completely (preventing voids) while the grooves themselves act as barriers that prevent solder from spreading beyond the disposition areas, thereby maintaining proper chip spacing.
Solution Approach 2:
The groove portions serve as intermediary structures between the disposition areas, mediating the solder flow. They provide a controlled pathway for solder to fill without spreading excessively, thus preventing both void formation and chip contact simultaneously.
Data Source
AI summary
A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.