Semiconductor Structure with Grounded Vias for Noise Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in issues such as poor electrical interconnection, high noise levels, and delamination, which cause yield loss and increase manufacturing costs due to material wastage and undesired configurations.
Innovation Solution
A semiconductor structure is developed with a polymeric layer between substrates and vertically extended conductive vias, where conductive vias connected to a signal source are surrounded by those connected to electrical ground, minimizing signal noise by optimizing the arrangement and configuration of conductive vias and pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor devices are miniaturized to increase functionality and integration, then device functionality and integration are improved, but manufacturing complexity increases leading to poor electrical interconnection, high noise levels, and delamination
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming conductive vias through substrates, depositing conductive materials, and creating isolated conductive regions. This segmentation allows complex interconnections to be built systematically through multiple simpler steps, resolving the manufacturing complexity issue while maintaining miniaturization benefits
Solution Approach 2:
The patent applies local quality by creating specific conductive configurations in different regions: signal conductive vias in first regions, ground conductive vias in second regions, and isolated conductive regions in third regions. This localized optimization addresses noise and interconnection issues specifically where they occur without affecting the entire device structure
2Speed
If conductive vias are densely packed to maintain signal transmission in miniaturized devices, then signal transmission is maintained, but noise levels increase and electrical interconnection quality deteriorates
Solution Approach 1:
The patent extracts ground conductive vias from the general conductive structure and places them in separate second regions adjacent to signal conductive vias. This separation extracts the noise-generating elements from proximity to signal paths, reducing electromagnetic interference while maintaining dense packaging for signal transmission
Solution Approach 2:
The patent creates isolated conductive regions and ground conductive vias beforehand to establish noise shielding structures before signal transmission paths are finalized. This prior cushioning with ground structures prevents noise from coupling into signal lines during operation
3Adaptability or versatility
If multiple manufacturing operations are implemented in miniaturized semiconductor devices, then device functionality is improved, but yield loss increases due to delamination and manufacturing defects
Solution Approach 1:
The patent performs preliminary actions by forming all conductive vias, depositing conductive materials, and creating isolated conductive regions before final assembly steps. This preliminary structuring ensures that interconnection paths are established and stabilized before subsequent manufacturing operations, reducing the risk of delamination and defects
Solution Approach 2:
The patent implements nested structures where conductive materials are deposited within conductive vias, and isolated conductive regions are formed within substrates. This nested configuration creates mechanically stable interconnections that resist delamination during multiple manufacturing operations while maintaining miniaturized functionality
Data Source
AI summary
A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first conductive via extended through the first substrate; a second conductive via extended through the first substrate; and a third conductive via extended through the first substrate, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, and the first conductive via and the third conductive via are configured to connect to an electrical ground.