Semiconductor Grounding via Through Silicon Vias
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Solution Overview
Problem
In traditional semiconductor packaging, the limited area of grounding pads restricts wire connection density, leading to difficulties in layout and signal transmission efficiency due to varying wire lengths, which can result in mismatched electricity between the chip and external grounding devices.
Innovation Solution
The method involves forming through silicon vias to expose grounding pads and filling a conductive layer on the back surface of the semiconductor substrate to connect them uniformly, increasing transmission density and efficiency using TSV technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding process is used to connect grounding pads to external grounding devices, then electrical connection is achieved, but the transmission distance varies causing electricity mismatch and reduced signal quality
Solution Approach 1:
The patent transitions from planar wire bonding on the chip surface to three-dimensional through-silicon via connections. By drilling vias through the substrate thickness, grounding pads are directly connected to the bottom surface, creating a vertical transmission path that eliminates long lateral wire routes and achieves uniform, short transmission distances for all grounding signals.
2Area of stationary object
If the area of grounding pads is limited, then chip size can be reduced, but the number of wires that can be connected to each grounding pad is restricted
Solution Approach 1:
The invention moves wire connections from the horizontal plane to the vertical dimension by forming through-silicon vias. Multiple wires can be bundled and routed through a single via or adjacent vias to reach grounding pads, effectively increasing the connection capacity per unit area without requiring larger pad areas.
Solution Approach 2:
Multiple wire connections are nested within or alongside the through-silicon vias structure. The vias act as conduits that can accommodate multiple wires or serve as part of a dense interconnect architecture where connections are stacked or bundled, maximizing the use of vertical space for multiple ground connections.
3Power
If more wires are connected to grounding pads to transmit high power current, then current transmission capacity increases, but layout becomes more difficult
Solution Approach 1:
The patent resolves layout complexity by transitioning to vertical through-silicon via connections. This dimensional change allows multiple high-current wires to be organized in a systematic vertical arrangement rather than requiring complex lateral routing across the chip surface, simplifying the overall interconnect layout while maintaining high current transmission capacity.
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.