Stacked Semiconductor Guard Ring for ESD Protection
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Solution Overview
Problem
High voltage integrated circuits face inefficiencies in electrostatic discharge (ESD) protection due to increased resistance between electrodes in high voltage wells, particularly in semiconductor fabrication processes that reduce design rules and isolation depth, impairing forward bias characteristics of diode devices.
Innovation Solution
A semiconductor device with a stack structure comprising a high voltage first conductivity type well, including a first and second conductivity type drift and impurity regions, isolated by a device isolation film, which reduces resistance without additional impurity injection steps, enhancing ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design rules are reduced and isolation depth is decreased in semiconductor fabrication, then manufacturing precision and productivity are improved, but resistance between electrodes in high voltage wells increases, worsening forward bias characteristics
Solution Approach 1:
The device is segmented into multiple regions with different doping types and concentrations. The high voltage well contains alternating doped regions (first conductivity type and second conductivity type) that create multiple depletion regions, effectively isolating adjacent devices while maintaining low resistance paths within each device structure.
Solution Approach 2:
Different regions of the semiconductor device are assigned different local properties through selective doping. The drift region has low doping concentration for high breakdown voltage, while the guard ring region has high doping concentration for low resistance, and the isolation regions have alternating doping types to provide both isolation and conductivity as needed in different locations.
2Reliability
If additional impurity injection steps are added to reduce resistance, then forward bias characteristic is improved, but device complexity and manufacturing time increase
Solution Approach 1:
Multiple functions are merged into single doping regions. The drift region simultaneously provides breakdown voltage control through its low doping concentration and serves as a conduction path. The guard ring region combines isolation functionality with low-resistance conduction through its high doping concentration, eliminating the need for separate isolation and conduction optimization steps.
Solution Approach 2:
The alternating doped regions in the high voltage well serve multiple functions: they provide electrical isolation between adjacent devices, create depletion regions for voltage blocking, and maintain low resistance paths for current flow. This multi-functionality reduces the need for additional specialized processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stack structure increases net doping of the guard ring, reducing resistance between the anode and cathode of the ESD protective device, thereby improving ESD protection efficiency.
Implementation Method 1
forming a first conductivity type well by injecting first conductivity type impurities into a semiconductor substrate; forming a first stack region having a first conductivity type drift region and a first conductivity type impurity region stacked in succession in the high voltage conductivity type well by injecting first conductivity type impurities into the first stack region
Data Source
AI summary
A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A second stack region may have a second conductivity type drift region, and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A device isolating film formed between the first stack region and the second stack region for isolating the first stack region from the second stack region.