Semiconductor Simulation via Hamiltonian Matrix Reduction
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Solution Overview
Problem
Current semiconductor device simulations require large memory and long calculation times due to the size of the Hamiltonian matrix, which is proportional to the number of atoms in the device, especially as channel lengths decrease to nanometers, necessitating a reduction in matrix size for efficient atom-level modeling.
Innovation Solution
The method involves extracting and reducing the Hamiltonian and overlap matrices using density functional theory (DFT) and tight-binding (TB) methods, applying a transformation matrix to orthonormalize Bloch states, removing unphysical branches, and calculating a final energy band structure and current characteristics with reduced matrix sizes, applicable to both homogeneous and heterogeneous semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full Hamiltonian matrix calculation is performed to achieve accurate quantum mechanical simulation, then calculation accuracy is improved, but memory requirement and calculation time increase significantly
Solution Approach 1:
The channel region is divided into multiple unit cells, each with its own Hamiltonian matrix. This segmentation allows the overall system to be analyzed through smaller, manageable sub-matrices rather than one large Hamiltonian, reducing memory requirements and computational complexity while maintaining accuracy through proper coupling of unit cell solutions.
Solution Approach 2:
Different unit cells can have different material compositions or structural characteristics (heterogeneous structures). The method allows each unit cell to be modeled with its specific local properties using DFT or TB methods, then combines these local solutions into a global energy band structure, achieving accurate local modeling without requiring a prohibitively large global matrix.
2Measurement precision
If a full Hamiltonian matrix calculation is performed to achieve accurate quantum mechanical simulation, then calculation accuracy is improved, but memory requirement increases significantly
Solution Approach 1:
The Hamiltonian is segmented into smaller unit cell Hamiltonians. Instead of storing and manipulating one large N×N Hamiltonian matrix for the entire device, the method stores and processes multiple smaller unit cell Hamiltonians, dramatically reducing memory footprint while preserving the ability to compute accurate energy band structures through iterative diagonalization of these smaller matrices.
3Measurement precision
If unphysical branches are removed through iterative band calculation, then energy band structure accuracy is improved, but additional calculation steps are required
Solution Approach 1:
The method intentionally allows unphysical branches to appear in the initial band calculation, then uses these spurious branches as indicators to guide the iterative removal process. By converting the harmful effect of unphysical branches into a diagnostic tool, the method systematically identifies and removes them through eigenvalue number convergence, ultimately achieving accurate energy band structures.
Solution Approach 2:
The iterative process uses feedback from eigenvalue number comparisons to control the removal of unphysical branches. The eigenvalue number serves as a feedback parameter that indicates whether unphysical branches remain, guiding the continuation or termination of the iterative calculation process and ensuring convergence to the correct physical solution.
Data Source
AI summary
Provided is a method for simulating a semiconductor device. The method includes extracting a Hamiltonian and an overlap matrix of a semiconductor device using a density functional theory or a tight-binding method, calculating each of Bloch states for each corresponding energy, obtaining a first reduced Hamiltonian and a first reduced overlap matrix with a reduced matrix size, and calculating a final transformation matrix and a final energy band structure in which all of unphysical branches, wherein the semiconductor device includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the channel region includes unit cells, each of which includes different material or has different structure.