Semiconductor Handling Jig for Precise Load Lock Registration
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Solution Overview
Problem
Existing substrate handling methods in semiconductor processing systems rely on expensive camera wafers for positioning, which require periodic calibration and are prone to inaccuracies due to user-dependent matchup and substrate slippage, limiting the precision of centering positions.
Innovation Solution
A jig comprising a disc body with fixation and verification pins is used to teach substrate handling, allowing precise alignment and registration with load locks and process chambers, eliminating the need for costly camera wafers and reducing inaccuracies by providing tactile and visual feedback for misregistration adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If camera wafers are used for teaching substrate handling positions, then positioning can be achieved, but the cost increases and periodic calibration is required
Solution Approach 1:
The patent replaces expensive camera wafers with inexpensive test substrates that can be easily replaced. The test substrate includes simple alignment features (marks or patterns) that can be manufactured at low cost, eliminating the need for costly camera wafers while maintaining positioning teaching functionality.
Solution Approach 2:
The patent creates a simplified copy of the substrate handling teaching function using test substrates with alignment marks instead of complex camera wafers. The alignment marks replicate the essential positioning reference function of camera wafers but with much lower cost and complexity.
2Ease of operation
If user-dependent matchup methods are used for positioning, then operation is flexible, but measurement precision deteriorates due to user experience variations
Solution Approach 1:
The patent enables the system to self-calibrate using automated image recognition of alignment marks on test substrates. The robot system automatically detects and learns the correct positioning based on objective mark detection rather than subjective user judgment, eliminating variability from user experience levels while maintaining operational simplicity.
Solution Approach 2:
The patent replaces manual user observation and adjustment with automated optical detection systems. Image recognition algorithms objectively measure alignment mark positions, substituting human visual judgment with machine vision that provides consistent, repeatable measurements independent of user skill level.
3Measurement precision
If silicon substrates are cycled through centering sensors for positioning, then centering can be established, but measurement precision is limited by substrate slippage during transfer
Solution Approach 1:
The patent performs positioning teaching before actual substrate processing using dedicated test substrates. The test substrates are specifically designed with alignment marks for teaching purposes, allowing the system to learn correct positions without the risk of slippage that would occur during normal substrate handling. This preliminary teaching phase separates the calibration function from the processing function.
Solution Approach 2:
The patent uses inexpensive test substrates dedicated solely for teaching and calibration purposes. These test substrates can be easily replaced if damaged during teaching operations, and their sole purpose is to provide stable alignment references without the risk of contaminating or damaging valuable production substrates.
Data Source
AI summary
A jig includes a disc body, a fixation pin, and a verification pin. The disc body has a first surface, an opposite a second surface, and a thickness separating the first surface from the second surface. A fixation aperture and a verification aperture extend through the thickness of the disc body and couple the first surface to the second surface of the disc body, the fixation aperture located radially outward of the verification aperture. The fixation pin is arranged to be slidably received within the fixation aperture to fix the disc body to an end effector within the semiconductor processing system. The verification pin is arranged to be slidably received within the verification aperture and supported by the disc body to indicate misregistration between the disc body and a load lock in the semiconductor processing system.


