Semiconductor Fine Pattern Formation via Hard Mask Etching

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Solution Overview

Problem

The challenge in semiconductor manufacturing is forming fine patterns with a reduced pitch, which is hindered by the resolution limitations of the photolithography process, making it difficult to achieve highly integrated semiconductor devices.

Innovation Solution

A method involving the formation of hard mask patterns in zigzag form using line and space patterns, where first and second hard mask patterns are created with specific pitches and etched to form openings that are transferred to a lower layer, allowing for the formation of fine patterns in a zigzag arrangement, thereby increasing the width of the patterns and optimizing pitch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photolithography process is used to form fine patterns, then manufacturing process is simple, but pattern resolution is limited and fine pitch cannot be achieved

Engineering Contradiction:
Improvepattern resolutionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the pattern formation process into multiple stages: first forming initial patterns, then using them as masks to create subsequent patterns. This segmentation allows achieving fine pitch that cannot be obtained through single-step photolithography, resolving the contradiction between manufacturing simplicity and pattern resolution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary pattern formation and mask creation before final pattern definition. By pre-forming hard masks and sacrificial patterns, the method enables subsequent steps to achieve higher resolution than direct photolithography would allow, addressing the resolution limitation while maintaining overall process feasibility.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If pattern pitch is reduced to increase integration, then device integration increases, but photolithography resolution limitation prevents pattern formation

Engineering Contradiction:
Improvedevice integrationVSAvoidpattern formation capability
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from two-dimensional planar patterning to three-dimensional vertical structure utilization. By forming patterns with varying thicknesses and using vertical profiles as masks, the method achieves effective pitch reduction and increased integration density beyond what conventional planar photolithography can provide.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested pattern formation where smaller patterns are formed within or between larger patterns through multiple masking steps. This nesting approach allows dense packing of features and achieves high integration by effectively reducing the functional pitch between active elements.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Quantity of substance

If multiple etching steps are performed to form zigzag patterns, then pattern density increases, but process complexity increases

Engineering Contradiction:
Improvepattern densityVSAvoidetching process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent combines multiple patterning functions into integrated mask structures and consolidated etching steps where possible. By merging the formation of adjacent patterns into single etch operations using shared masks, the method increases pattern density while mitigating the increase in process complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs self-aligned patterning where previously formed patterns automatically serve as masks for subsequent etching steps. This self-service approach increases pattern density through precise alignment while reducing the need for additional alignment and masking operations, thereby limiting the increase in process complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8785319B2Methods for forming fine patterns of a semiconductor device
Publication Date: 2014.07.22 SAMSUNG ELECTRONICS CO LTD
  • US8785319B2 patent drawing
  • US8785319B2 patent drawing
  • US8785319B2 patent drawing

AI summary

Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.