Semiconductor Device Outermost Periphery Hetero Region Current Distribution
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Solution Overview
Problem
Conventional semiconductor devices with switch structures experience uneven current distribution, leading to higher current density and faster deterioration at the outermost switch structure, which limits their reliability and destruction resistance.
Innovation Solution
The semiconductor device incorporates a P+ polycrystalline silicon outermost periphery hetero semiconductor region with a higher energy barrier, reducing current flow in the outermost switch structure and distributing current more evenly across basic cells, thereby improving long-term reliability and destruction resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switch structures are arranged on the semiconductor chip, then the device can function as a switch, but the current density of the outermost switch structure becomes higher than other portions, causing current concentration and rapid deterioration
Solution Approach 1:
The patent applies local quality by forming an outermost periphery hetero semiconductor region with different material composition (P+ polycrystalline silicon) compared to the basic hetero semiconductor regions. This creates a localized difference in energy barrier height at the periphery, where the P+ region provides a higher energy barrier to reduce current concentration, while the basic regions maintain normal switching function. This local modification resolves the contradiction by addressing the harmful current concentration effect specifically at the outermost portion without affecting the overall device functionality.
2Productivity
If the outermost switch structure is used for switching, then the device achieves compact design, but the outermost switch structure deteriorates more rapidly due to higher current density
Solution Approach 1:
The patent differentiates the outermost periphery hetero semiconductor region from the basic hetero semiconductor regions by using P+ polycrystalline silicon with higher impurity concentration. This creates a localized energy barrier modification that reduces current flow through the outermost switch structure, thereby extending its operational lifetime while maintaining the compact design and switching efficiency of the overall device.
Solution Approach 2:
The patent converts the harmful effect of current concentration at the outermost region into a beneficial feature by intentionally designing the P+ periphery region to have higher energy barrier. This higher barrier, which would normally be seen as an obstruction, actually serves to redistribute current more evenly across the device, protecting the outermost switch structure from excessive current stress and extending its lifetime while maintaining overall switching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces current concentration in the outermost switch structure, enhancing the semiconductor chip's reliability and ability to withstand overcurrent and overvoltage, while maintaining efficient conduction and interruption performance.
Implementation Method 1
an outermost periphery hetero semiconductor region 9 of P +[0022] The portion of the hetero semiconductor region 3 adjoined to the gate insulation film 4 is referred to as a heterojunction driving end 3a of a heterojunction interface 23 between the drift region 2 and the hetero semiconductor region 3.
Implementation Method 2
the energy barrier heights of the outermost periphery hetero semiconductor region 9 and the drift region 2 are higher than the energy barrier heights of the hetero semiconductor region 3 and the drift region 2
Data Source
Figure 1~2
Figure 3A~3B
Figure 4A~4B
AI summary
A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure.