Semiconductor Device High-Resistance Blocking Layer Routing
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently creating high-resistance layers for nanometer-scale devices, which are crucial for advanced semiconductor devices but require precise control and integration with conductive and dielectric layers to enhance device performance and density.
Innovation Solution
A semiconductor device and manufacturing method involving a high-resistance layer over a dielectric layer, with a plug layer connecting conductive portions, where the high-resistance layer acts as a blocking layer to prevent exposure and improve routing, allowing for increased gate density and precise electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-resistance layer is formed over conductive portions to provide electrical isolation, then electrical isolation and routing are improved, but the manufacturing process complexity increases due to additional layer formation and patterning steps
Solution Approach 1:
The high-resistance layer is formed to serve multiple functions simultaneously: it provides electrical isolation between conductive portions, acts as a blocking layer during subsequent patterning operations to prevent unwanted etching, and serves as a foundation for forming plug portions. This multi-functionality reduces the need for separate dedicated layers for each function, thereby simplifying the overall manufacturing process despite the added complexity of high-resistance layer formation.
Solution Approach 2:
The high-resistance layer is formed in advance before the patterning and plug formation steps. By having this layer pre-formed, it is already in position to provide electrical isolation and to serve as a blocking layer when etching patterns are created. This preliminary action ensures that the isolation function is established before subsequent manufacturing steps, preventing potential short circuits and simplifying the sequence of operations.
2Productivity
If the high-resistance layer is used as a blocking layer during patterning, then routing precision and gate density are improved, but the manufacturing precision requirements increase
Solution Approach 1:
The high-resistance layer acts as an intermediary blocking layer during the patterning process. When etching patterns are formed to create recesses, the high-resistance layer prevents the etchant from reaching and affecting the underlying conductive portions that should remain protected. This intermediary function allows for more aggressive or complex patterning operations to be performed with higher precision, as the blocking layer provides a buffer that protects critical underlying structures while allowing the desired patterns to be formed in the dielectric and oxide layers above.
3Adaptability or versatility
If multiple layers (dielectric, high-resistance, oxide) are formed over conductive portions, then electrical isolation and routing flexibility are enhanced, but the device structure complexity increases
Solution Approach 1:
The device structure is segmented into multiple functional layers: a dielectric layer for primary insulation, a high-resistance layer for electrical isolation and blocking functions, and an oxide layer for additional insulation and pattern definition. Each layer is segmented to perform its specific function, allowing the routing to be planned and formed through specific combinations of these layers. This segmentation provides routing flexibility as conductive portions can be connected through plugs that navigate through selected layers, while maintaining electrical isolation where needed.
Solution Approach 2:
The multiple layers add a vertical dimension to the routing architecture. Instead of relying solely on planar routing, the high-resistance layer and oxide layer create additional vertical pathways and isolation planes. Plugs can be formed to connect conductive portions by passing through specific combinations of layers at different vertical positions, providing routing flexibility in three dimensions. This vertical dimensionality allows for more complex interconnections while maintaining clear electrical isolation boundaries between different conductive elements.
Data Source
AI summary
A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.