Semiconductor Device High-Voltage Gate Electrode Etching Control
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Solution Overview
Problem
Conventional semiconductor device fabrication methods face challenges in controlling etching steps for forming word lines and high-voltage transistors, leading to over etching or excess residue due to limited process windows, and require additional ion implantation processes to achieve desired breakdown voltages.
Innovation Solution
A semiconductor device and method where a substrate with distinct memory, high-voltage, and logic areas are fabricated using a first and second conductive layer, with the high-voltage gate electrode having a thickness substantially greater than the logic gate electrode, allowing precise etching control and eliminating the need for additional ion implantations by using a reticle with improved transmission rate for endpoint detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a reticle with lower transmission rate is used for forming word lines of NVM device, then the etching can be performed, but the process window is reduced making it difficult to control the etching stop point
Solution Approach 1:
The patent divides the substrate into distinct memory area, high-voltage area, and logic area with separate processing flows. The etching process is segmented into multiple steps with different reticles: a first reticle for high-voltage transistor gate electrodes and logic transistor gate electrodes, and a second reticle for NVM word lines. This segmentation allows each etching step to use an optimized reticle with appropriate transmission rate, resolving the contradiction between etching control and transmission rate requirements.
2Ease of manufacture
If identical reticles are used for etching polysilicon to form gate electrodes of logic element and high-voltage transistor, then manufacturing cost is reduced, but additional ion implantation processes are required to achieve predetermined breakdown voltage
Solution Approach 1:
The patent applies local quality by forming gate electrodes with different thicknesses in different areas of the substrate. The high-voltage transistor gate electrode is formed with a greater thickness than the logic transistor gate electrode through selective etching processes. This local differentiation in gate electrode thickness allows the high-voltage transistor to achieve the required breakdown voltage without additional ion implantation processes, while logic transistors maintain their standard characteristics.
3Device complexity
If the high-voltage gate electrode has the same thickness as the logic gate electrode, then the fabrication process is simplified, but additional ion implantation is needed to reach breakdown voltage
Solution Approach 1:
The patent implements preliminary action by forming the high-voltage gate electrode with a greater thickness from the outset, before any ion implantation processes would be needed. The etching process is designed to selectively remove polysilicon to different depths in different areas, creating the thicker high-voltage gate electrode in advance. This preliminary thickness differentiation eliminates the need for subsequent ion implantation to achieve the required breakdown voltage.
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of memory cells, a logic gate electrode and a high-voltage gate electrode. The substrate at least includes a memory area, a high-voltage area and a logic area. The memory cells are disposed in the memory area. The logic gate electrode is disposed on the logic area. The high-voltage gate electrode has a first portion and a second portion in contact with each other and stacked on the high-voltage area. The high-voltage gate electrode has a thickness substantially greater than that of the logic gate electrode.