Semiconductor Hole Patterns Using Multi-Layer Mask Segmentation

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Solution Overview

Problem

Current semiconductor manufacturing techniques face challenges in forming hole patterns with pitches or diameters smaller than the minimum resolution of photolithography processes, limiting the integration density and complexity of semiconductor devices.

Innovation Solution

A method involving sequential stacking and selective removal of mask layers to form inner and outer spacers, patterning barrier patterns, and core insulating patterns, allowing for the creation of high-density hole patterns without requiring advanced photolithography processes, using materials like silicon nitride and polycrystalline silicon.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photolithography process is used for forming hole patterns, then manufacturing process is simple, but minimum resolution limits pitch and diameter of hole patterns

Engineering Contradiction:
Improvepitch and diameter of hole patternsVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The mask layer is divided into multiple discrete mask patterns (first mask pattern, second mask pattern, third mask pattern) that are formed sequentially. Each mask pattern defines a different set of holes, allowing the formation of high-density hole patterns with smaller pitch and diameter by combining multiple patterning steps rather than relying on a single photolithography exposure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer mask layer is formed and prepared in advance before the patterning mask layers are applied. This preliminary buffer mask layer serves as a foundation that enables subsequent selective removal processes to create the desired hole patterns with high precision, allowing the photolithography process to be used for forming the buffer mask while achieving higher precision in the final hole patterns through the multi-stage masking process.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple mask layers are sequentially stacked and selectively removed, then high-density hole patterns are formed, but process steps increase

Engineering Contradiction:
Improvehole pattern densityVSAvoidfabrication efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The buffer mask layer serves multiple functions: it acts as a foundation for the patterning mask layers, provides a reference structure for selective removal, and enables the formation of both first and second hole patterns through different masking configurations. This multi-functionality reduces the need for additional dedicated layers, partially compensating for the increased process steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patterning mask layers (first, second, and third mask patterns) are temporarily formed and then selectively removed to create the desired hole patterns. These mask layers are discarded after serving their patterning function, allowing the underlying buffer mask layer to be recovered and reused for defining the final hole patterns. This approach enables high-density patterning while managing process complexity through systematic mask removal and recovery.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS9159560B2Methods of forming hole patterns of semiconductor devices
Publication Date: 2015.10.13 SAMSUNG ELECTRONICS CO LTD
  • US9159560B2 patent drawing
  • US9159560B2 patent drawing
  • US9159560B2 patent drawing

AI summary

A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern.