Semiconductor Hole Pattern Design for Dimensional Error Control
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Solution Overview
Problem
Conventional methods of designing semiconductor integrated circuit layouts with hole patterns on a virtual grid smaller than the resolution pitch limit lead to increased dimensional errors in the resist pattern due to the high density of hole patterns, causing amplification factors beyond the desired range.
Innovation Solution
A method is introduced where a grid with an interval smaller than the minimum permissible pitch is used, with hole patterns arranged only on specific lattice points, and an upper limit is set for the number of hole patterns in the surrounding lattice points to control the amplification factor, thereby reducing the circuit pattern area and dimensional errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a virtual grid with interval smaller than minimum permissible pitch is used to arrange hole patterns, then flexibility in arrangement is improved and circuit pattern area is reduced, but dimensional error in resist pattern becomes larger
Solution Approach 1:
The patent applies local quality by differentiating between different regions around each hole pattern. It defines an arrangement restricted region where the number of hole patterns is controlled, while other regions can have more flexible arrangements. This localized control allows the circuit pattern area to be minimized while keeping dimensional errors within acceptable ranges by restricting hole pattern density only in critical local areas.
Solution Approach 2:
The patent changes the parameter of hole pattern density by introducing an upper limit on the number of hole patterns within a predetermined distance from each hole pattern. This parameter control transforms the arrangement strategy from uniform dense packing to controlled variable density, thereby reducing dimensional errors while maintaining overall area efficiency.
2Area of stationary object
If multiple hole patterns are arranged densely on a small grid, then circuit pattern area is reduced, but amplification factor of dimensional error increases beyond desired range
Solution Approach 1:
The patent implements local quality control by defining arrangement restricted regions around each hole pattern where the density of adjacent hole patterns is limited. This localized density control prevents excessive amplification factors in critical areas while allowing efficient space utilization in non-critical areas, thus maintaining reliability without sacrificing area efficiency.
Solution Approach 2:
The patent employs feedback by establishing an upper limit rule that monitors and controls the number of hole patterns within a predetermined distance from each hole pattern. This feedback mechanism ensures that the amplification factor remains within the desired range of four to five by adjusting the arrangement density based on the counted number of adjacent hole patterns.
3Productivity
If hole patterns are arranged on all lattice points of a fine grid, then productivity of layout design is improved, but dimensional accuracy deteriorates
Solution Approach 1:
The patent applies local quality by introducing arrangement restricted regions around each hole pattern where the number of adjacent hole patterns is controlled. This localized restriction maintains high productivity through automated arrangement while preventing dimensional accuracy deterioration by controlling hole pattern density in critical local areas where amplification factors could become excessive.
Solution Approach 2:
The patent changes the arrangement parameter by imposing an upper limit on hole pattern density within a predetermined distance from each hole pattern. This parameter modification allows automated high-productivity layout design to proceed while ensuring dimensional accuracy is maintained by preventing excessive hole pattern clustering that would amplify dimensional errors.
Data Source
AI summary
A method of designing a pattern of a hole pattern having a configuration, in which grid of interval smaller than a minimum permissible pitch according to a design rule for a semiconductor integrated circuit is provided in a pattern drawing, a hole pattern is arranged on a first lattice point which is an intersection of the grid, and, at the same time, other hole patterns are not arranged on a second lattice point group which is on the periphery of the first lattice point, and is adjacent to the first lattice point is provided. And, the number of hole patterns, which may be arranged in a third lattice point group of a plurality of lattice points which are on the periphery of a second lattice point group and are within a predetermined distance from the first lattice point, is controlled.