Semiconductor Integrated Circuit High-Pass Filter Eye Opening

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-speed data transmission between a transmission device and a reception device is hindered by significant waveform rounding and inter-symbol interference due to transmission line characteristics, leading to a narrow 'eye' waveform opening, which existing methods like Half UI-spaced FFE attempt to address but complicate circuit configurations by requiring higher frequency or multi-phase clock signals.

Innovation Solution

A semiconductor integrated circuit configuration that includes a high-pass filter to reduce low-frequency components in delayed input data, allowing for digital-to-analog conversion and signal processing to widen the eye waveform opening without the need for complex clock signals, using a simpler configuration similar to 1 UI-spaced FFE.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If Half UI-spaced FFE is used to raise the gain of frequency higher than the Nyquist frequency, then the opening of the eye waveform is greatly opened, but the circuit configuration becomes complicated and the circuit scale increases due to requiring a clock signal having twice the frequency or multi-phase clock signals

Engineering Contradiction:
Improveeye waveform openingVSAvoidcircuit configuration
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the clock signal frequency parameter from twice the FFE frequency (in Half UI-spaced FFE) to the same frequency as the FFE. This parameter change allows achieving similar eye waveform opening while using a simpler circuit configuration without requiring multi-phase clock signals or higher frequency clocks

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts and eliminates the complex clock signal generation requirements (multi-phase clocks or double-frequency clocks) from the Half UI-spaced FFE configuration, retaining only the essential FFE functionality with a simplified single-clock architecture that achieves comparable performance

Inventive Principle:
Principle #2Taking out (Extraction)

2Speed

If transmission line is used for high-speed data transmission, then data can be transmitted between devices, but waveform rounding and inter-symbol interference occur due to transmission loss characteristic that attenuates high frequency components

Engineering Contradiction:
Improvedata transmission speedVSAvoidwaveform quality
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent converts the harmful effect of transmission line attenuation (which preferentially attenuates high frequency components) into a benefit by using a feed-forward equalizer that raises the gain of high frequency components above the Nyquist frequency, thereby compensating for the attenuation and restoring waveform quality

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent implements a feedback mechanism through the equalizer that continuously compensates for the transmission line's frequency-dependent attenuation, using the known characteristics of the transmission loss to adjust and equalize the frequency response, thereby maintaining waveform integrity despite the attenuating channel

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11223378B2Semiconductor integrated circuit, transmission device, and control method of transmission device
Publication Date: 2022.01.11 KIOXIA CORP
  • US11223378B2 patent drawing
  • US11223378B2 patent drawing
  • US11223378B2 patent drawing

AI summary

A semiconductor integrated circuit includes a first circuit configured to carry out digital-to-analog conversion on input data; a high-pass filter configured to reduce a component, the component having a frequency lower than a predetermined cutoff frequency, in delayed input data obtained by delaying the input data, and output the delayed input data; a second circuit configured to carryout the digital-to-analog conversion on the delayed input data that passes through the high-pass filter; and a third circuit configured to drive a transmission signal, the transmission signal based on an addition signal obtained by adding an output signal of the first circuit and an output signal of the second circuit.