Semiconductor High Voltage Generator Clock Control

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Solution Overview

Problem

Conventional high voltage generators in semiconductor devices waste power by keeping the oscillator enabled during active operating time, even when pumping operations are not performed, leading to unnecessary current consumption.

Innovation Solution

A high voltage generator that controls the oscillator to generate clock signals only when at least one high voltage pump is performing a pumping operation, using enable signals to synchronize the clock signal generation with the pumping activities, thereby reducing unnecessary power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the oscillator is kept enabled during active operating time, then clock signals are continuously available for high voltage pump operations, but unnecessary current is consumed when pumping operations are not performed

Engineering Contradiction:
Improveclock signal availabilityVSAvoidoscillator current consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The oscillator operates periodically rather than continuously, being enabled only during initial pumping times of program and read operations. The clock encoder generates enable signals that activate the oscillator only when high voltage pump operations are required, eliminating continuous operation during inactive periods and thereby reducing power consumption while maintaining clock availability when needed.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If the oscillator is enabled only during pumping operations, then current consumption is reduced, but clock signals may not be available when needed

Engineering Contradiction:
Improveoscillator current consumptionVSAvoidclock signal availability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The clock encoder monitors the operational state of the high voltage pump units and generates enable signals for the oscillator based on actual pumping activity. This feedback mechanism ensures the oscillator is activated only when clock signals are actually required for pumping operations, guaranteeing clock availability during necessary operations while minimizing unnecessary operation and current consumption.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If multiple high voltage pump units operate independently, then each pump can be optimized for specific voltage levels, but the oscillator must remain enabled for any potential pumping operation

Engineering Contradiction:
Improvevoltage generation flexibilityVSAvoidoscillator power waste
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The clock encoder combines the enable signals from multiple high voltage pump units into a single coordinated control mechanism. By merging the operational status information from first and second high voltage pump units, the system generates a unified enable signal for the oscillator, allowing multiple pumps to operate independently for different voltage levels while the oscillator is activated only when any pump requires clock signals, thereby reducing power waste.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7623394B2High voltage generating device of semiconductor device
Publication Date: 2009.11.24 SK HYNIX INC
  • US7623394B2 patent drawing
  • US7623394B2 patent drawing
  • US7623394B2 patent drawing

AI summary

A high voltage generator of a semiconductor device includes a first high voltage pump unit, a second high voltage pump unit, and a clock signal generating unit. The first high voltage pump unit compares a first high voltage and a first reference voltage to generate a first enable signal, and performs a pumping operation in response to the first enable signal and a first clock signal to generate the first high voltage. The second high voltage pimp unit compares a second high voltage and a second reference voltage to generate a second enable signal, and perform a pimping operation in response to the second enable signal and a second clock signal to generate the second high voltage. The clock signal generating unit generates the first clock signal or the second clock signal in response to the first enable signal and the second enable signal when at least one of the first enable signal and the second enable signal is enabled.