Semiconductor Layout for Uniform HV-LV Gate Height Integration
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Solution Overview
Problem
The integration of high-voltage and low-voltage components on a semiconductor device poses challenges due to size constraints and process limitations, particularly in achieving uniform height and avoiding loading effects, which affect device performance.
Innovation Solution
The semiconductor device design includes active areas for high-voltage components within the periphery of low-voltage components, with a gate dielectric layer of the high-voltage component partially embedded in the interlayer dielectric layer of the low-voltage component, and shallow trench isolations of equal depth, allowing for a simplified fabrication process and uniform height across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-voltage and low-voltage components are integrated on a single chip, then cost is reduced and operating efficiency is improved, but height differences and loading effects occur between regions
Solution Approach 1:
The patent applies local quality by creating different dielectric layer structures in different regions of the chip. The high-voltage region has a first interlayer dielectric layer with a first thickness, while the low-voltage region has a second interlayer dielectric layer with a second thickness. This regional differentiation allows each component type to have optimized electrical characteristics while maintaining overall chip integration, thereby resolving the height uniformity issue without sacrificing operating efficiency.
Solution Approach 2:
The patent resolves the height difference problem by transitioning from a two-dimensional planar structure to a three-dimensional layered structure. By stacking multiple interlayer dielectric layers with different thicknesses in different regions, the patent creates vertical dimensionality that compensates for the height differences between high-voltage and low-voltage components, eliminating loading effects while maintaining integration benefits.
2Area of stationary object
If device size is reduced to improve integration density, then more components fit on chip, but process limitations and loading effects increase
Solution Approach 1:
The patent applies segmentation by dividing the chip into distinct high-voltage and low-voltage regions, each with its own optimized process parameters and dielectric layer structures. This segmentation allows independent optimization of each region without compromising the other, reducing process complexity despite high integration density. The method defines specific active areas for high-voltage components within the periphery region of low-voltage components, enabling precise control over each segment's fabrication.
3Adaptability or versatility
If shallow trench isolations are formed at different depths to accommodate different component types, then component functionality is achieved, but loading effects occur
Solution Approach 1:
The patent applies equipotentiality by creating a reference plane through the composite interlayer dielectric structure. The first and second interlayer dielectric layers are configured to provide equivalent electrical isolation potential at different depths, ensuring that both high-voltage and low-voltage components experience consistent electrical boundaries. This eliminates loading effects between regions while maintaining the depth variations needed for different component functionalities.
Data Source
AI summary
A method of fabricating semiconductor device, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.