Semiconductor Layout for HV-LV Transistor Height Uniformity
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Solution Overview
Problem
The integration of high-voltage and low-voltage components on a semiconductor device poses challenges due to size reduction, where it becomes difficult to coexist high-voltage components like fin field-effect transistors, leading to height differences and loading effects, affecting device performance.
Innovation Solution
The active areas of high-voltage components are placed in the periphery of low-voltage components, with the high-voltage component's gate dielectric layer partially embedded in the interlayer dielectric layer of the low-voltage component, and shallow trench isolations are formed to achieve uniform height and depth, simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-voltage components and low-voltage components are integrated on the same chip, then cost is reduced and operating efficiency is improved, but height differences and loading effects occur affecting device performance
Solution Approach 1:
The patent applies local quality by creating different structural configurations in different regions of the chip. The high-voltage component region has a gate dielectric layer embedded in the interlayer dielectric layer to achieve uniform height, while the low-voltage component region maintains its standard finFET structure. This localized structural adaptation allows both high-voltage and low-voltage components to coexist without height differences and loading effects, resolving the contradiction between integration benefits and device performance.
2Volume of moving object
If device size is reduced to improve integration density, then manufacturing cost decreases, but it becomes difficult to dispose high-voltage components and fin field-effect transistors on the same semiconductor device
Solution Approach 1:
The patent resolves the size reduction contradiction by transitioning from a planar two-dimensional layout to a three-dimensional vertical structure. The gate dielectric layer of the high-voltage component is embedded within the interlayer dielectric layer, creating a vertical stacking arrangement. This dimensional change allows both high-voltage and low-voltage components to be disposed on the same chip with smaller footprint while maintaining proper spacing and avoiding manufacturing difficulties.
3Manufacturing precision
If high-voltage component gate dielectric layer is embedded in low-voltage component interlayer dielectric layer, then uniform height is achieved avoiding loading effects, but fabrication process complexity increases
Solution Approach 1:
The patent applies merging by combining the formation of the high-voltage component gate dielectric layer with the existing interlayer dielectric layer structure. Instead of creating separate processing streams, the gate dielectric layer is integrated into the interlayer dielectric layer formation process. This merging approach achieves uniform height between high-voltage and low-voltage regions while minimizing additional fabrication process complexity.
Data Source
AI summary
A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.