Semiconductor Package Hybrid Bonding Patterned Substrate
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Solution Overview
Problem
The high cost and stringent constraints of hybrid-bonding in semiconductor packaging, particularly due to non-uniform dishing and erosion responses of conductive and dielectric features after chemical mechanical polishing (CMP), lead to unsatisfactory bonding results when applied to regions with different line widths, affecting the yield of packaged products.
Innovation Solution
A semiconductor package structure with a patterned substrate featuring distinct regions for hybrid-bonding and non-hybrid bonding, where the first die is hybrid-bonded to a region with conductive features adapted for line widths less than 20 nm, and the second die is bonded using flip-chip or wire bonding to a region with conductive features suitable for those methods, allowing for differential dishing and erosion control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hybrid-bonding is applied to all regions, then bonding precision is improved for narrow line widths, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The substrate surface is divided into multiple regions with different line width characteristics. Each region is assigned an appropriate bonding method: hybrid-bonding for narrow line width regions (first region) and conventional bonding for wider line width regions (second region). This segmentation allows optimization of bonding precision where needed while avoiding unnecessary complexity in other areas.
Solution Approach 2:
Different bonding methods are applied to different regions based on their specific line width requirements. The first region with narrow conductive features receives hybrid-bonding for high precision, while the second region with wider features uses conventional bonding. This local quality approach ensures each region gets the appropriate bonding technique without imposing uniform complexity across the entire substrate.
2Manufacturing precision
If hybrid-bonding is applied to all regions, then bonding precision is improved for narrow line widths, but manufacturing cost increases
Solution Approach 1:
The substrate is segmented into regions requiring hybrid-bonding and regions suitable for conventional bonding. This segmentation ensures hybrid-bonding is applied only where its superior precision is necessary for narrow line widths, reducing overall manufacturing cost while maintaining required bonding precision in critical areas.
Solution Approach 2:
The bonding method parameter is changed based on regional line width characteristics. Narrow line width regions (first region) use hybrid-bonding for high precision, while wider line width regions (second region) use conventional bonding methods. This parameter change optimizes the balance between bonding precision and manufacturing cost by avoiding unnecessary hybrid-bonding in regions where it is not required.
3Device complexity
If single bonding operation is used for all dies, then process simplicity is maintained, but bonding reliability decreases for mixed line width regions
Solution Approach 1:
The substrate surface is segmented into different bonding regions with distinct line width characteristics. This segmentation enables application of appropriate bonding methods to each region, improving bonding reliability for narrow line width features while maintaining process simplicity through a single integrated substrate structure.
Solution Approach 2:
Different bonding methods are applied to different regions based on local line width requirements. The first region with narrow conductive features receives hybrid-bonding for high reliability, while the second region with wider features uses conventional bonding. This local quality approach ensures bonding reliability is optimized where needed without requiring completely separate processing systems.
4Manufacturing precision
If CMP planarization is performed, then surface flatness is improved for hybrid-bonding, but non-uniform dishing and erosion occur in regions with different line widths
Solution Approach 1:
The substrate is segmented into regions with different line width characteristics before CMP planarization. This allows the CMP process to be optimized for each region's specific requirements, reducing non-uniform dishing and erosion. The first region with narrow features and the second region with wider features can have their CMP parameters adjusted to achieve uniform surface flatness without excessive dishing or erosion in either region.
Solution Approach 2:
CMP planarization parameters are adjusted based on local line width characteristics in different regions. The first region with narrow conductive features receives CMP treatment optimized for maintaining feature integrity and minimizing dishing, while the second region with wider features receives CMP treatment optimized for achieving surface flatness. This local quality approach to CMP process control reduces non-uniform dishing and erosion across the entire substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective bonding across regions with varying line widths, improving the yield and reliability of semiconductor packages by optimizing bonding techniques based on specific line width requirements, thereby reducing manufacturing complexities and costs.
Implementation Method 1
the dielectric feature and the conductive feature on each surface are prepared by a planarization operation, for example, a chemical mechanical polishing (CMP) operation
Data Source
AI summary
A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.