Semiconductor Hybrid Bonding Thermal Stress Mitigation
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Solution Overview
Problem
The bonding of wafers using hybrid bonding methods faces issues due to thermal stress caused by the large mismatch in coefficients of thermal expansion (CTEs) between metal pads and dielectric layers, leading to structural instability and defects.
Innovation Solution
A semiconductor structure is designed with conductive pads and filling material layers that have a smaller width than the conductive lines, are aligned and coplanar, and include soft materials like carbon-containing benzocyclobutene, which absorb thermal stress, and an optional air gap for expansion, to prevent delamination of dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal pads are used in hybrid bonding, then electrical conductivity is improved, but thermal stress increases due to CTE mismatch with dielectric layers
Solution Approach 1:
The patent applies local quality by creating a filling material layer with specific mechanical properties (higher CTE) only in the region surrounding the metal pad, while the rest of the dielectric layer maintains its original properties. This localized modification allows the filling material to specifically counteract thermal stress at the stress-concentrated pad region without affecting the overall structure.
Solution Approach 2:
The patent uses composite materials by combining the metal pad with a surrounding filling material layer made of carbon-containing material (such as BCB). This composite structure leverages the high conductivity of metal and the high CTE of carbon-containing material to simultaneously achieve electrical conductivity and thermal stress mitigation.
2Reliability
If metal pads with large CTE are used, then electrical connection is achieved, but structural stability deteriorates due to thermal stress
Solution Approach 1:
The patent applies beforehand cushioning by pre-installing the filling material layer around the metal pad before bonding occurs. This filling material acts as a cushion that absorbs and distributes thermal stress during subsequent thermal cycles, preventing structural instability and defects before they can occur.
Solution Approach 2:
The patent changes the local mechanical parameters (specifically CTE) by introducing a filling material with higher CTE than the dielectric layer. This parameter change in the filling material allows it to expand more during heating, thereby compensating for the stress generated by the metal pad's CTE mismatch with the dielectric.
3Manufacturing precision
If conductive pads are made smaller than conductive lines, then bonding precision is improved, but stress concentration increases
Solution Approach 1:
The patent applies local quality by creating a filling material layer that specifically surrounds the conductive pad region. This localized filling material provides stress distribution exactly where needed (at the pad-dielectric interface) without affecting the overall bonding precision achieved through the smaller pad design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor structure effectively mitigates thermal stress-induced damage and delamination by using soft filling material layers and an air gap to absorb expansion stresses, enhancing the stability and reliability of the bonded dielectric layers.
Implementation Method 1
the metal pads have higher coefficients of thermal expansion (CTEs) than the surrounding dielectric layers at the surfaces of the bonded wafers. This results in problems for the bonding of the surface dielectric layers. Further, structural instability and some defects may occur owing to a thermal stress induced by the large mismatch of CTEs.
Implementation Method 2
The first filling material layer and the second filling material layer respectively include soft material. The first filling material layer and the second filling material layer respectively include carbon contained material.
Data Source
AI summary
A semiconductor structure includes a first component and a second component bonded thereof. The first component includes a first dielectric layer, a first conductive structure, and a first filling material layer. The first conductive structure is in the first dielectric layer and includes a first conductive line and a first conductive pad thereon. The first filling material layer is on the first conductive line and surrounds the first conductive pad. The second component includes a second dielectric layer, a second conductive structure, and a second filling material layer. The second dielectric layer is bonded to the first dielectric layer. The second conductive structure is in the second dielectric layer, and includes a second conductive pad bonded to the first conductive pad. The second filling material layer surrounds the second conductive pad and in contact with a second conductive line on the second conductive pad.