Semiconductor Device Hybrid Bonding Vertical Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of a cell array and control circuit in semiconductor devices requires separate bonding regions outside the cell array, leading to increased chip size due to the need for conductive lines to extend and connect with the control circuit, which complicates wafer bonding and increases the device size.
Innovation Solution
A semiconductor device with a hybrid bonding structure that includes conductive lines at different levels, allowing for direct coupling within the cell array region through contacts, reducing the need for external bonding regions and minimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate bonding regions are formed outside the cell array to connect lower layer conductive lines to the control circuit, then the control circuit can be integrated with the cell array, but the chip size increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive lines at different levels (first level and second level) within the cell array region. Lower layer conductive lines are connected to upper layer conductive lines through vertical contacts, enabling three-dimensional routing that eliminates the need for horizontal extension outside the cell array boundary.
Solution Approach 2:
The patent implements nested conductive line structures where upper layer conductive lines are positioned over lower layer conductive lines within the same cell array footprint. This nesting allows multiple conductive paths to be stacked vertically, maximizing space utilization and keeping all connections within the original cell array boundaries.
2Reliability
If conductive lines extend outside the cell array region to connect to the control circuit, then connectivity is achieved, but the device complexity increases
Solution Approach 1:
The patent merges the functions of multiple conductive lines by having upper layer conductive lines extend over lower layer conductive lines within the cell array region. This consolidation allows both lower and upper layer connections to be established through vertical contacts at the same location, reducing the number of separate bonding regions needed.
Solution Approach 2:
The patent segments conductive lines into different vertical levels, with lower layer conductive lines at a first level and upper layer conductive lines at a second level. This segmentation allows independent routing and connection of each layer through dedicated contacts, simplifying the overall connectivity architecture while maintaining robust connections.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes at least one row line arranged in a first direction over a cell array region, and at least one column line arranged in a second direction intersecting the first direction over the cell array region. The row line and the column line are configured to include conductive lines located at different levels and coupled to each other through a contact in the cell array region.