Semiconductor IC-Embedded Substrate Wet Blasting
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Solution Overview
Problem
Conventional methods for embedding semiconductor ICs with narrow electrode pitches into substrates face challenges such as increased package size, complexity in forming multiple layers for mechanical strength, misalignment of pad electrodes and wiring patterns, and difficulties in reducing module thickness due to the need for thicker substrates and precise laser irradiation processes.
Innovation Solution
A method involving the use of layered resin layers with conductive protrusions, where the semiconductor IC is mounted on one resin layer and covered by another, with alignment marks for precise positioning, and the resin layer thickness is reduced using wet blasting to expose the protrusions, allowing for thinner substrates and preventing short-circuit defects by setting the wiring pattern width smaller than the protrusion diameter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a cavity is formed in a printed circuit board to embed a semiconductor IC, then the module thickness can be reduced, but the substrate thickness must be increased to maintain structural strength
Solution Approach 1:
The substrate is divided into a first substrate portion and a second substrate portion connected by a bridge portion. The semiconductor IC is embedded in the first substrate portion while the bridge portion maintains structural integrity, allowing the embedded region to be thinner than the overall substrate thickness.
Solution Approach 2:
The connection structure transitions from a planar cavity embedding to a three-dimensional configuration where the bridge portion extends in the thickness direction, creating a stepped structure that resolves the conflict between local thinning and global strength requirements.
2Manufacturing precision
If the cavity size is increased to accommodate the semiconductor IC, then the IC can be properly embedded, but misalignment occurs between the pad electrode and wiring pattern
Solution Approach 1:
The semiconductor IC is mounted on a mounting board before substrate formation. This preliminary mounting allows precise positioning and alignment to be established early in the process, ensuring that the pad electrodes align with the wiring patterns even when the final substrate geometry is optimized for thickness reduction.
3Productivity
If laser irradiation is used to expose each pad electrode, then the IC can be embedded, but processing time increases in proportion to the number of pad electrodes
Solution Approach 1:
Multiple pad electrode exposure operations are merged into a single collective exposure step. The mounting board configuration and resin layer design allow all pad electrodes to be exposed simultaneously rather than individually, dramatically reducing the total processing time while maintaining the required precision for narrow electrode pitches.
4Manufacturing precision
If the electrode pitch is reduced to 100 μm or less, then higher integration is achieved, but the via diameter must be reduced making desmearing difficult
Solution Approach 1:
The mechanical desmearing process for narrow vias is replaced with an alternative approach using the mounting board and resin layer configuration. The design allows pad electrodes to be exposed through the resin without requiring small-diameter vias, thereby maintaining ease of manufacture while achieving narrow electrode pitches through optimized mounting and exposure geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the precise and efficient embedding of semiconductor ICs with narrow electrode pitches, reducing the overall thickness of the substrate, minimizing misalignment, and preventing short-circuit defects, while allowing for high-precision mounting and reduced processing time.
Implementation Method 1
the resin layer thickness is reduced using wet blasting to expose the protrusions
Data Source
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AI summary
A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the semiconductor IC 120, and a second resin layer 112 for covering the back surface 120b of the semiconductor IC 120. The stud bumps 121 of the semiconductor IC 120 protrude from the surface of the first resin layer 111. The method for causing the stud bumps 121 to protrude from the surface of the first resin layer 111 may involve using a wet blasting method to cause an overall reduction of the thickness of the first resin layer 111. The stud bumps 121 can thereby be properly uncovered even when the electrode pitch of the semiconductor IC 120 is narrow.