Semiconductor Identification Key Generation via Probabilistic Via Shorts
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Solution Overview
Problem
Conventional Physical Unclonable Function (PUF) technologies face challenges in ensuring sufficient randomness and stability of identification keys due to spatial and temporal process variations, leading to biased output probabilities and yield issues, making them vulnerable to attacks and difficult to implement with low manufacturing costs.
Innovation Solution
A semiconductor-based identification key generating device and method that uses a plurality of unit cells with probabilistically determined shorts between conductive layers, adjusting etching characteristics to ensure balanced digital values of 0 and 1, generating an identification key through a combination of digital values from selected unit cells, which are invariant over time and resistant to external attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PUF technology is used to generate identification keys, then hardware fingerprinting is achieved, but output bit probability becomes biased due to spatial and temporal process variations
Solution Approach 1:
The patent changes the physical parameters of the etching process (etching time, etching rate, etching conditions) to control the shorting probability of vias. By adjusting these parameters, the system achieves balanced output bit probability (close to 50% for both 0 and 1) while maintaining identification key stability across different manufacturing batches and temporal variations.
Solution Approach 2:
The patent implements a feedback mechanism where the actual shorting probability is measured and used to adjust the etching parameters for subsequent production. This closed-loop control ensures that output bit probability remains balanced even when process conditions vary, resolving the contradiction between manufacturing variability and output quality.
2Productivity
If via size is reduced to increase PUF capacity, then more identification keys can be generated, but output bit probability bias increases due to process variations
Solution Approach 1:
Instead of simply reducing via size to increase capacity, the patent changes the etching parameters (time, rate, conditions) to precisely control the shorting probability. This allows maintaining balanced output bits even with smaller via sizes, enabling higher PUF capacity without sacrificing probability balance.
3Reliability
If etching characteristics are adjusted to balance digital values, then randomness is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent adjusts etching parameters (time, rate, conditions) to achieve balanced digital values. While this requires process control, the adjustments are made within the existing etching framework rather than introducing entirely new manufacturing steps, thereby improving randomness while limiting the increase in manufacturing complexity.
Data Source
AI summary
The present invention provides an identification key generating device and an identification key generating method. The identification key generating device comprises: a plurality of unit cells provided on a circuit in a semiconductor manufacturing procedure; a reading unit for reading for shorting of each of the unit cells; a digital value generation unit for determining the probability for the shorting of each of the unit cells, and generating a digital value of each of the unit cells on the basis of the reading for shorting from the reading unit; and a selection unit for selecting at least one of the plurality of unit cells, wherein an identification key is generated from a combination of respective digital values generated from the unit cells selected by means of the selection unit.