Semiconductor Identification Circuit Using Intermediate Voltage
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Solution Overview
Problem
Existing semiconductor devices face challenges in generating unique identification information for each chip without increasing chip area, as existing methods require multiple latch circuits to achieve sufficient bit length, leading to space inefficiency.
Innovation Solution
A semiconductor device with an identification information generation circuit that includes a power supply control circuit and a memory array, utilizing a power supply control circuit to output intermediate voltages to memory cells, which are determined by the threshold voltages of MOS transistors, allowing for random data generation based on these voltages, thereby reducing the need for multiple latch circuits and conserving chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple latch circuits are used to generate identification information with sufficient bit length, then the identification information quality is improved, but the chip area increases
Solution Approach 1:
The patent changes the operating voltage parameter of the memory cell from standard supply voltage to an intermediate voltage (e.g., half of the supply voltage). This parameter change enables the memory cell to generate random data based on threshold voltage variations of MOS transistors, achieving sufficient identification information quality without requiring multiple latch circuits, thus reducing chip area.
Solution Approach 2:
The patent uses the inherent physical characteristics (threshold voltage variations) of existing memory cell components to generate identification information, rather than adding separate latch circuits. This approach copies the functionality of identification generation from dedicated circuits to the memory cell itself, reducing overall chip area while maintaining identification quality.
2Area of stationary object
If the power supply control circuit outputs intermediate voltage to memory cells, then the chip area is reduced, but the circuit complexity increases
Solution Approach 1:
The power supply control circuit is designed to serve multiple functions: it controls the standard power supply to the memory array and simultaneously generates the intermediate voltage for identification information generation. This multi-functionality reduces the need for separate dedicated circuits, thereby reducing overall chip area while managing circuit complexity through functional integration.
Solution Approach 2:
The patent merges the identification information generation function with the existing memory cell structure and power supply control circuit. By combining these functions rather than adding separate dedicated circuits, the overall chip area is reduced while the increased complexity is localized to the integrated control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the generation of chip-specific identification information efficiently, improving reproducibility and reducing chip area requirements by leveraging the variations in threshold voltages of MOS transistors within the memory cells.
Implementation Method 1
utilizing a power supply control circuit to output intermediate voltages to memory cells, which are determined by the threshold voltages of MOS transistors, allowing for random data generation based on these voltages
Data Source
AI summary
A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.