Semiconductor Device Impurity Segmentation for IDSS Stability
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Solution Overview
Problem
Conventional semiconductor devices, such as junction field effect transistors (J-FETs), experience variations in saturated drain-source current (IDSS) and increased noise due to excessive diffusion of p-type impurities, leading to inconsistent chip performance and deteriorated electrical characteristics like forward transfer admittance and voltage gain.
Innovation Solution
A semiconductor device with a p-type semiconductor substrate acting as a back gate, featuring a channel region of n-type conductivity, source and drain regions, and an n-type impurity region of higher concentration beneath the gate electrode, which maintains uniform impurity concentration and reduces the influence of p-type impurity diffusion, thereby stabilizing the current path resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate region is formed with high-concentration p-type impurity, then the gate region can effectively control the channel, but the p-type impurity excessively diffuses into the channel region causing IDSS variation and noise increase
Solution Approach 1:
The channel region is divided into a first channel region (below the gate region) and a second channel region (other portions). The first channel region has a lower impurity concentration to maintain low resistance and good electrical characteristics, while the second channel region has a higher impurity concentration to resist p-type impurity diffusion from the gate region. This segmentation allows different parts of the channel to serve different functions.
Solution Approach 2:
Different impurity concentrations are applied to different spatial locations within the channel region. The first channel region directly below the gate region maintains low impurity concentration for optimal electrical performance, while the second channel region has higher impurity concentration to prevent excessive diffusion. This local quality differentiation resolves the contradiction between gate control effectiveness and IDSS consistency.
2Reliability
If the channel region impurity concentration is increased to prevent p-type impurity diffusion, then diffusion resistance is reduced, but the breakdown voltage decreases
Solution Approach 1:
The channel region is segmented into two zones with different impurity concentrations. The first channel region below the gate region maintains low impurity concentration to ensure high breakdown voltage, while the second channel region has higher impurity concentration to provide sufficient diffusion resistance against p-type impurity from the gate. This segmentation enables both requirements to be satisfied simultaneously in different locations.
Solution Approach 2:
The impurity concentration is optimized locally for different functional requirements. The first channel region has low impurity concentration for high breakdown voltage strength, while the second channel region has high impurity concentration for diffusion resistance. This local quality approach resolves the contradiction between diffusion resistance and breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces IDSS variation among chips within a single wafer, decreases noise voltage, and enhances forward transfer admittance and voltage gain by maintaining uniform resistance and breakdown voltage characteristics.
Implementation Method 1
the p type impurity in the gate region diffuses into the channel region having a lower impurity concentration; the n type impurity concentration is decreased in the portion right below the gate region
Data Source
AI summary
An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.