Semiconductor Device with ILD Stress Layer for Strain Control
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Solution Overview
Problem
Current semiconductor device fabrication methods for multi-gate field effect transistors (MUGFETs) face challenges in efficiently forming channel regions with optimal strain for enhanced electron and hole mobility, particularly in integrating multiple gate structures and achieving precise control over dopant distribution and stress memorization regions.
Innovation Solution
The method involves forming fin structures, isolation structures, and dummy gate structures on a substrate, followed by gate spacer formation, fin recess, source/drain region creation, and an anneal process to induce strain in the channel region, which includes forming an interlayer dielectric (ILD) stress layer and replacing the dummy gate with a metal gate structure, ensuring precise control over the channel region's strain and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple gate structures are integrated in MUGFETs, then control over current flow is improved, but device complexity increases
Solution Approach 1:
The device is segmented into multiple fins (e.g., four fins) with isolation structures between them, allowing each fin to be independently formed and controlled. This segmentation enables multiple gate structures to be integrated while maintaining manageable complexity through modular fabrication processes.
Solution Approach 2:
The gate electrode structure serves multiple functions: it controls current flow through all fins simultaneously, acts as a common control terminal for multiple gate surfaces, and provides electrical connection across the channel region. This multi-functionality reduces the need for separate control mechanisms for each gate.
2Reliability
If strain is induced in the channel region to enhance mobility, then electron and hole mobility are improved, but manufacturing precision requirements increase
Solution Approach 1:
The strain in the channel region is controlled by adjusting parameters such as the thickness and material composition of the ILD stress layer. By changing these parameters, the desired strain level can be achieved without requiring extremely precise manufacturing tolerances, as the strain is inherently built into the structure during fabrication.
Solution Approach 2:
The ILD stress layer acts as an intermediary element that introduces strain into the channel region indirectly. Instead of applying strain directly to the channel (which would require high precision), the stress layer serves as a mediator that transfers controlled stress to the channel through its mechanical coupling, relaxing manufacturing precision requirements.
3Reliability
If dopant distribution is precisely controlled in source and drain regions, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
Different dopant types and concentrations are applied to different regions: n-type dopants are used in source/drain regions of nFETs, while p-type dopants are used in source/drain regions of pFETs. This local differentiation allows precise control of dopant distribution tailored to each region's specific electrical requirements without requiring a single complex doping process.
Solution Approach 2:
The source and drain regions are formed with appropriate doping before the final gate structure is completed. This preliminary doping action allows the dopant distribution to be established early in the process when the channel region is still accessible, simplifying subsequent steps and reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved electron and hole mobility by creating compressive strain in the channel region, enhancing the performance of both nFET and pFET devices through precise dopant distribution and stress management, leading to more efficient semiconductor device operation.
Implementation Method 1
an anneal process to induce strain in the channel region
Implementation Method 2
forming an interlayer dielectric (ILD) stress layer proximate the top portion of gate structure and over the ILD layer... creating compressive strain in the channel region
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.