Semiconductor Device Impedance Adjustment Layer for Signal Delay
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased parasitic capacitance between wirings, resulting in signal delay (RC delay) issues due to reduced pitch between wiring patterns.
Innovation Solution
Incorporating an impedance adjustment layer, specifically made of VO2, between wirings to compensate for parasitic capacitance by functioning as a parallel LC circuit, reducing signal delay and enabling effective impedance adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between wirings is reduced to increase integration, then higher integration is achieved, but parasitic capacitance increases causing signal delay
Solution Approach 1:
An impedance adjustment layer is introduced as an intermediary between adjacent wirings to control and adjust the impedance characteristics. This intermediary layer compensates for parasitic capacitance effects and reduces signal delay while maintaining reduced pitch for high integration
Solution Approach 2:
The impedance adjustment layer modifies the electrical parameters (impedance, capacitance) of the wiring structure by introducing a material with specific dielectric properties. This parameter change allows compensation for parasitic capacitance and reduction of RC delay while maintaining reduced wiring pitch
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The impedance adjustment layer effectively reduces signal delay by compensating for phase delays, allowing for faster signal propagation and supporting the miniaturization of semiconductor device structures.
Implementation Method 1
The reduction of the pitch between the wirings in the semiconductor device increases parasitic capacitance between the wirings
Implementation Method 2
an impedance adjustment layer, specifically made of VO2, between wirings to compensate for parasitic capacitance by functioning as a parallel LC circuit
Data Source
AI summary
There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.