Semiconductor Device Impurity Distribution Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with a P-type semiconductor layer, an N-type semiconductor layer, and an intrinsic layer face a trade-off between low ON-resistance and fast switching speed, as high hole injection into the intrinsic layer slows down the transition from the ON-state to the OFF-state.
Innovation Solution
The semiconductor device incorporates a P-type anode layer with a recess portion and an outer edge portion, where the impurity distribution is controlled to optimize hole injection into the intrinsic layer, allowing for adjustable ON-resistance and switching speed, while also enhancing breakdown immunity by forming a guard ring layer with a similar impurity distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amount of holes injected into the low-concentration layer from the P-type semiconductor layer is increased, then the ON-resistance is reduced, but the switching speed from the ON-state to the OFF-state becomes slower
Solution Approach 1:
The P-type semiconductor layer is divided into a first P-type semiconductor layer and a second P-type semiconductor layer with different impurity concentrations. The first layer has a higher impurity concentration to provide sufficient holes for low ON-resistance, while the second layer has a lower impurity concentration to enable faster switching speed. This local differentiation of impurity concentration resolves the contradiction between low ON-resistance and fast switching speed.
2Reliability
If the impurity concentration in the P-type semiconductor layer is increased to reduce ON-resistance, then the hole injection amount increases, but the breakdown immunity decreases
Solution Approach 1:
The semiconductor device employs a multi-layer structure where the first P-type semiconductor layer has high impurity concentration for low ON-resistance, while the second P-type semiconductor layer has lower impurity concentration to maintain breakdown immunity. The low-concentration layer between the P-type and N-type layers also contributes to breakdown protection. This spatial distribution of different impurity concentrations simultaneously achieves low ON-resistance and high breakdown immunity.
3Speed
If the switching speed is increased by reducing hole injection, then the transition from ON-state to OFF-state becomes faster, but the ON-resistance increases
Solution Approach 1:
The first P-type semiconductor layer with high impurity concentration ensures sufficient hole injection for low ON-resistance during the ON-state, while the second P-type semiconductor layer with lower impurity concentration and the low-concentration layer facilitate rapid carrier removal during the OFF-state transition, achieving fast switching speed. The differentiated local properties of each layer resolve the contradiction between low ON-resistance and fast switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively balances ON-resistance and switching speed, and increases the breakdown immunity of the terminal portion, enabling the semiconductor device to handle currents up to two to three times the rated current without material melting or electric field concentration.
Implementation Method 1
when the amount of holes injected into the low-concentration layer from the P-type semiconductor layer is high, the ON-resistance is lower; but the switching speed from the ON-state to the OFF-state is slower
Implementation Method 2
it is important to adequately control the injection amount of the holes into the low-concentration layer
Data Source
AI summary
A semiconductor device includes second and third semiconductor layers provided on a first semiconductor layer. The second semiconductor layer includes a recess portion and an outer edge portion. The third semiconductor layer is away from the second semiconductor layer in a first direction along a first boundary between the first semiconductor layer and the recess portion. The second semiconductor layer has first and second distributions of a second conductivity type impurity at a vicinity of the first boundary and at a vicinity of a second boundary between the outer edge portion and the first semiconductor layer, respectively. The third semiconductor layer has a third distribution of a second conductivity type impurity at a vicinity of a third boundary between the first semiconductor layer and the third semiconductor layer. The first distribution is substantially same as the second distribution. The third distribution is substantially same as the second distribution.