Semiconductor Device Impurity Gradient Switching Loss
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Solution Overview
Problem
Semiconductor devices face challenges in reducing switching loss and current leakage when transitioning from ON to OFF state due to trap levels that increase ON resistance and current leakage, while also needing to minimize carrier injection.
Innovation Solution
A semiconductor device design with a p-type semiconductor layer having distinct regions of varying p-type impurity concentrations and thicknesses, where the first region with higher impurity concentration forms an Ohmic contact and the second region with lower impurity concentration forms a Schottky contact, reducing hole injection and trap levels, and optimizing the area ratio to minimize switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If trap levels are formed in the semiconductor to shorten carrier lifetime, then switching loss is reduced, but current leakage increases in the OFF state
Solution Approach 1:
The patent applies local quality by creating a non-uniform impurity concentration distribution within the semiconductor layer. Specifically, the impurity concentration is set to be higher near the first electrode and lower near the second electrode, forming different local regions with distinct electrical characteristics. This gradient structure allows trap levels to be effectively utilized for carrier removal in regions where it benefits switching performance, while maintaining lower leakage in other regions, thus resolving the contradiction between reducing switching loss and minimizing current leakage.
2Loss of time
If trap levels are formed to eliminate carriers faster, then turn-off period is shortened, but ON resistance increases
Solution Approach 1:
The patent implements local quality through a spatially varying impurity concentration profile where the concentration decreases from the first electrode toward the second electrode. This creates regions with different carrier lifetimes and resistance characteristics along the current path. The higher impurity concentration region near the first electrode provides sufficient carriers for low ON resistance, while the gradient structure enables faster carrier elimination in the turn-off region, thus achieving both short turn-off period and acceptable ON resistance.
Solution Approach 2:
The patent applies parameter changes by systematically varying the impurity concentration parameter throughout the semiconductor layer. The concentration is optimized to decrease from approximately 1×10^18 atoms/cm³ near the first electrode to lower values near the second electrode. This parameter gradient enables dynamic control of carrier lifetime and resistance characteristics, allowing the semiconductor to exhibit different electrical properties during ON and OFF states, thereby resolving the contradiction between fast turn-off and low ON resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively shortens the turn-off period, reduces switching loss, and minimizes current leakage by controlling carrier density and trap levels, thereby optimizing ON resistance and switching performance.
Implementation Method 1
the first region with higher impurity concentration forms an Ohmic contact
Implementation Method 2
the second region with lower impurity concentration forms a Schottky contact, reducing hole injection
Data Source
AI summary
A semiconductor device includes a semiconductor body, an electrode provided on a surface of the semiconductor body. The semiconductor body includes a first semiconductor layer and a second semiconductor layer provided between the first semiconductor layer and the second electrode. The second semiconductor layer includes first and second regions arranged along the surface of the semiconductor body. The first region has a surface contacting the electrode, and the second region includes second conductivity type impurities with a concentration lower than a concentration of the second conductivity type impurities at the surface of the first region. The second semiconductor layer has a first concentration of second conductivity type impurities at a first position in the second region, and a second concentration of second conductivity type impurities at a second position between the first position and the electrode, the second concentration being lower than the first concentration.