Semiconductor Device Impurity Profile for Short-Channel Effect Suppression
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Solution Overview
Problem
The short-channel effect in semiconductor devices, caused by shortening the gate length of transistors, leads to increased off current and deterioration of switching operation due to halo ion-implantation affecting the entire source/drain region, resulting in reduced driving force and increased parasitic capacitor resistance.
Innovation Solution
A semiconductor device structure where a first conductive impurity region is formed on both sides of the gate electrode, extending into the semiconductor substrate, with a lower impurity concentration in the overlapping portion with the source/drain region, and a method involving ion-implantation through a mask with a space for the side-wall of the gate electrode to create a concentration profile that suppresses the short-channel effect while minimizing impact on the source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length of the transistor is shortened to increase driving force and lower gate capacitor, then the operation speed is improved, but the threshold voltage is lowered and off current increases due to short-channel effect
Solution Approach 1:
The patent applies local quality by creating a non-uniform impurity concentration distribution in the channel region. Specifically, a high-concentration impurity region is formed at the lower channel region near the source/drain junctions, while the upper channel region maintains lower concentration. This localized high concentration suppresses the short-channel effect at the critical junction areas without degrading the overall threshold voltage characteristics of the transistor, thereby enabling high-speed operation with improved reliability.
2Reliability
If halo ion-implantation is performed to suppress short-channel effect, then the channel concentration is increased and channel depth is shallowed, but the source/drain region becomes high concentration throughout, increasing diffusion layer capacity and resistance
Solution Approach 1:
The patent employs local quality by precisely controlling the impurity concentration distribution through selective ion implantation geometry. The implantation is designed to create high concentration only in the lower channel region adjacent to source/drain junctions, while deliberately avoiding high concentration in the source/drain regions themselves. This localized approach suppresses the short-channel effect where needed without introducing the harmful high concentration in source/drain regions that would increase diffusion layer capacity and resistance.
Solution Approach 2:
The patent applies segmentation by dividing the channel region into distinct concentration zones: a high-concentration lower channel region for short-channel effect suppression and a lower-concentration upper channel region for maintaining good threshold voltage and low resistance characteristics. This segmentation of the impurity profile allows independent optimization of different functional requirements within the same transistor structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the short-channel effect, reduces diffusion layer capacity, and decreases resistance, enabling high-speed operation by maintaining a high channel concentration while minimizing the impact on the source/drain region, thus improving the switching operation of the transistor.
Implementation Method 1
ion-implanting a first conductive impurity into the surface of the semiconductor substrate through the space from a direction inclined with a prescribed angles for perpendicular to the surface of the semiconductor substrate to form the first conductive impurity region
Data Source
AI summary
According to the present invention, there is provided a semiconductor device including a first conductive type semiconductor substrate, a gate electrode formed over the semiconductor substrate via a gate insulator, a first conductive impurity region buried in the semiconductor substrate, the first conductive impurity region being both sides of an extend plane, the extend plane being extended from side-walls of the gate electrode into the semiconductor substrate and a second conductive type source/drain region partially overlapping with the first conductive impurity region and extending from an end of the gate electrode at the semiconductor substrate to an outer region in the semiconductor substrate, wherein a first conductive impurity concentration at a prescribed depth in the overlapping portion between the first conductive impurity region and the source/drain region is lower than the first conductive impurity concentration in the first conductive impurity region except the overlapping portion corresponding to the prescribed depth.