Semiconductor Device With Inclined Lower Layer Structure
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Solution Overview
Problem
In three-dimensional stacked semiconductor memory devices, the stepwise formation of conductive layers leads to significant depth differences between contact plugs, causing connection failures, increased electrical resistance, and parasitic capacitance, while also prolonging etching processes and limiting downscaling of terrace regions.
Innovation Solution
The formation of a lower layer inclined structure with continuously inclined or stepped surfaces allows for the creation of terrace regions on the semiconductor device, reducing the depth difference between contact plugs and enabling efficient connection, reducing etching time, and allowing for downscaled chip areas through lithography and dry etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to connect to conductive layers in a stepwise stacked body, then connection to conductive layers is achieved, but depth difference between contact plugs increases causing connection failures and increased electrical resistance
Solution Approach 1:
The patent introduces a lower layer inclined structure that tilts the terrace regions relative to the substrate surface. This dimensional change in the substrate preparation stage allows contact plugs to be formed at more uniform depths by adjusting the inclination angle, thereby reducing depth differences and improving connection reliability without compromising electrical performance
2Productivity
If stepwise formation of conductive layers is used, then three-dimensional stacked structure is achieved, but etching process time is prolonged
Solution Approach 1:
The patent applies preliminary action by forming the lower layer inclined structure and terrace regions before stacking the conductive layers. This pre-preparation creates optimized etching conditions that allow for faster, more uniform etching processes later, significantly reducing overall etching time while maintaining the three-dimensional stacked structure
3Area of stationary object
If terrace regions are downscaled to reduce chip area, then chip size is reduced, but connection reliability deteriorates due to increased electrical resistance and parasitic capacitance
Solution Approach 1:
By tilting the terrace regions at optimized inclination angles, the patent enables smaller contact plug diameters to achieve the same connection reliability as larger plugs on flat surfaces. This dimensional adjustment reduces parasitic capacitance and electrical resistance, allowing chip area downscaling without compromising connection performance
4Area of stationary object
If contact plug diameter is reduced to enable downscaling, then chip area decreases, but electrical resistance increases causing connection failures
Solution Approach 1:
The inclined structure compensates for the increased aspect ratio of smaller contact plugs by tilting the terrace regions. This allows smaller diameter contact plugs to maintain uniform depth formation and acceptable electrical resistance, enabling chip downscaling without connection failures
Data Source
AI summary
A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.