Semiconductor Device With Indium Alloy Stress Absorption
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Solution Overview
Problem
The reliability of semiconductor devices is compromised due to stress generated between substrates with different linear expansion coefficients, particularly when using Au—Sn alloy, which has high hardness and fails to absorb thermal stress, leading to damage in connection portions.
Innovation Solution
A semiconductor device design that includes a silicon substrate, copper posts, and indium layers between the semiconductor element and the substrate, forming Au—In and Cu—In alloy layers to absorb thermal stress, thereby preventing damage and ensuring reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If Au—Sn alloy is used to connect substrates with different linear expansion coefficients, then the connection strength is improved, but the reliability deteriorates due to high hardness and inability to absorb thermal stress
Solution Approach 1:
The patent segments the single Au—Sn alloy layer into multiple layers with different compositions and functions: a first alloy layer (Au—Sn) providing connection strength, and a second alloy layer (Au—In or Cu—In) providing stress absorption capability. This segmentation allows each layer to optimize its specific function rather than requiring a single material to satisfy conflicting requirements.
Solution Approach 2:
The patent applies local quality by giving different regions (layers) different material properties: the first alloy layer has high hardness and strength for mechanical connection, while the second alloy layer has low melting point and high ductility for stress absorption. Each layer's properties are optimized for its specific location and function in the overall connection structure.
2Strength
If Au—Sn alloy is used to connect substrates, then the mechanical strength is improved, but the reliability deteriorates due to stress concentration at connection portions
Solution Approach 1:
The patent divides the connection structure into segmented layers: a first alloy layer for mechanical strength and a second alloy layer for stress distribution. This segmentation prevents stress concentration by distributing thermal and mechanical stresses across multiple interfaces and materials with different properties, rather than concentrating them in a single Au—Sn layer.
Solution Approach 2:
The patent employs composite materials by combining Au—Sn alloy with Au—In or Cu—In alloy in a layered structure. This composite construction leverages the high strength of Au—Sn while incorporating the stress-absorbing capabilities of the second alloy, creating a connection structure that achieves both mechanical strength and reliability under thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device effectively absorbs thermal stress between the silicon substrate and the semiconductor element, preventing breaks and ensuring high reliability by using copper and indium layers that can bend and absorb the stress caused by differing linear expansion coefficients.
Implementation Method 1
stress generated between the substrates by heating or heat generation
Implementation Method 2
indium layers that can bend and absorb the stress
Implementation Method 3
copper post connected to one surface of the silicon substrate
Data Source
AI summary
There is provided a semiconductor device. The semiconductor device includes: a silicon substrate; a copper post connected to one surface of the silicon substrate; a semiconductor element having a linear expansion coefficient different from that of the silicon substrate; a metal layer provided between the semiconductor element and the silicon substrate to cover the copper post; a first alloy layer provided between the copper post and the semiconductor element, wherein the first alloy layer includes alloy of gold and a metal of the metal layer; and a second alloy layer provided between the metal layer and the semiconductor element, wherein the second alloy layer includes alloy of gold and the metal of the metal layer.