Semiconductor Package Inductive Lateral Interconnects
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Solution Overview
Problem
Impedance mismatch in integrated circuit packages leads to signal degradation in high-speed data connections due to parasitic capacitance, which existing methods attempt to address by voiding, increasing package form factor and layer count.
Innovation Solution
Incorporating lateral interconnects with arc or spiral segments around vertical interconnects to introduce inductive circuitry, increasing self-inductance and matching impedance without increasing package size or layer count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voiding is used to reduce parasitic capacitance and improve impedance matching, then impedance matching is improved, but package form factor and layer count increase
Solution Approach 1:
The patent changes the electrical parameters of the existing package structure by introducing lateral interconnects with specific geometries (arc segments, spiral segments) that modify the inductance and capacitance values. This allows impedance matching to be achieved through parameter adjustment rather than structural expansion via voiding.
Solution Approach 2:
The lateral interconnects act as intermediary elements between the vertical interconnects, introducing controlled inductance to compensate for parasitic capacitance. These intermediary structures enable impedance matching without requiring the signal paths to be separated through voiding.
2Reliability
If voiding is used to reduce parasitic capacitance and improve impedance matching, then impedance matching is improved, but device complexity increases
Solution Approach 1:
The patent achieves impedance matching by changing the electrical parameters (inductance, capacitance) through geometric modifications of existing interconnect structures rather than adding new layers or complex voiding patterns. The arc and spiral segments provide parameter tuning capability within the existing package architecture.
Solution Approach 2:
The lateral interconnects serve multiple functions: they provide electrical connection between signal lines and simultaneously introduce the necessary inductance for impedance matching. This multi-functionality eliminates the need for separate impedance-matching structures that would increase layer count.
3Reliability
If lateral interconnects with arc or spiral segments are added to increase self-inductance, then impedance matching is improved, but parasitic capacitance increases
Solution Approach 1:
The patent converts the harmful effect of increased parasitic capacitance (from adding lateral interconnects) into a beneficial outcome by carefully designing the geometry to achieve the desired impedance match. The total inductance and capacitance changes work together to achieve impedance matching, transforming what could be a harmful parameter increase into a useful design degree of freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal integrity by reducing reflection noise and maintaining impedance matching, as evidenced by increased self-inductance and decreased mutual inductance, while slightly increasing parasitic capacitance, thereby improving electrical performance without increasing package size or layer count.
Implementation Method 1
Incorporating lateral interconnects with arc or spiral segments around vertical interconnects to introduce inductive circuitry, increasing self-inductance and matching impedance
Implementation Method 2
impedance mismatch in integrated circuit packages may degrade an efficacy of high speed links
Data Source
AI summary
Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.