Semiconductor Device Inductor Capacitor Integration
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Solution Overview
Problem
Conventional semiconductor devices with overlapping inductor and capacitor elements in multilayer wiring layers face inadequate wiring resources, leading to increased size due to the need for bypass wiring, especially when the capacitor element is formed in a different layer, resulting in a larger device footprint.
Innovation Solution
The semiconductor device integrates the capacitor element in the same layer as the inductor elements, with the capacitor formed inside the inductor elements in plan view, reducing the need for additional wiring resources and allowing for a more compact design by eliminating the need for bypass wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the capacitor element is formed in a different layer from the inductor element in multilayer wiring layer, then the inductor element and capacitor element can be overlapped in plan view to reduce device size, but wiring resources become inadequate in the region where both elements are formed
Solution Approach 1:
The patent merges the capacitor element into the same wiring layer as the inductor element, allowing both elements to share the same layer space. This eliminates the need for separate layer allocation and enables sufficient wiring resources in the region where both elements coexist, resolving the contradiction between device miniaturization and wiring resource adequacy.
Solution Approach 2:
The capacitor element is positioned inside the inductor element in plan view, creating a nested configuration where the capacitor is contained within the spatial footprint of the inductor. This nested arrangement maximizes space utilization and allows both elements to share the same layer without conflicting wiring resource requirements.
2Stability of the object's composition
If the capacitor element is formed in a different layer from the inductor element, then layer separation is achieved, but bypass wiring must be formed to connect transistors, increasing device size
Solution Approach 1:
The patent combines the capacitor element with the inductor element in the same wiring layer, eliminating the need for bypass wiring to connect transistors. This merging approach removes the additional wiring paths that would increase device footprint, while still achieving proper layer separation through the integrated design.
3Device complexity
If the capacitor element is formed outside the inductor element in plan view, then wiring resources are sufficient, but the device footprint increases
Solution Approach 1:
The patent positions the capacitor element inside the inductor element in plan view, creating a nested configuration that maximizes space utilization. This nested arrangement allows both elements to share the same layer with adequate wiring resources while minimizing the overall device footprint, as the capacitor occupies the internal space of the inductor rather than requiring additional external area.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.