Semiconductor Inductor Capacitor Overlapping Footprint Integration

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Solution Overview

Problem

Current semiconductor devices face challenges in minimizing series resistance and parasitic capacitance, which affect the performance of RF circuits and voltage-controlled oscillators, due to the separate components of inductors and capacitors.

Innovation Solution

A semiconductor device design that integrates an inductor coil with a capacitor arrangement, where the capacitor is electrically coupled to the inductor coil, allowing for overlapping footprints and sharing of parasitic capacitance with the substrate, thereby reducing series resistance and parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate inductor and capacitor components are used, then device complexity is reduced and ease of manufacture is improved, but series resistance increases and parasitic capacitance worsens performance

Engineering Contradiction:
Improvequality factorVSAvoidcomponent integration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines separate inductor and capacitor components into a single integrated structure where the capacitor is formed within the inductor footprint. The capacitor electrodes are positioned between the inductor windings or beneath the inductor coil, allowing both components to occupy overlapping spatial regions. This merging reduces the overall device area and minimizes parasitic effects while maintaining electrical performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The capacitor structure is nested within the inductor footprint by positioning capacitor electrodes in the spaces between inductor windings or beneath the inductor coil. This nesting approach allows the capacitor to be embedded within the inductor's spatial envelope, achieving high integration density without increasing the overall device area.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If inductor and capacitor footprints overlap, then area is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice footprintVSAvoidalignment tolerance
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent resolves footprint overlap challenges by utilizing vertical layering and three-dimensional positioning. Capacitor electrodes are placed in different vertical layers relative to the inductor windings, with dielectric materials separating the components. This dimensional approach allows footprint overlap without requiring extremely tight lateral alignment tolerances.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If capacitor arrangement shares parasitic capacitance with substrate, then parasitic capacitance is reduced, but series resistance increases

Engineering Contradiction:
Improvequality factorVSAvoidseries resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the typically harmful parasitic capacitance between the capacitor and substrate into a beneficial shared capacitance. By designing the capacitor arrangement to intentionally share parasitic capacitance with the substrate, the patent reduces the total parasitic capacitance affecting the resonant circuit, thereby improving the quality factor. The substrate's parasitic capacitance is utilized rather than treated as an unwanted effect.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This integration enhances the quality factor of the LC resonant circuit, improves current consumption, and expands the tuning range of voltage-controlled oscillators by minimizing series resistance and parasitic capacitance.

Implementation Method 1

an inductor coil including a winding

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Implementation Method 2

a capacitor arrangement including at least one capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

at least a portion of the parasitic capacitance between the inductor coil and the substrate is shared with at least a portion of the parasitic capacitance between the capacitor arrangement and the substrate

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS7906831B2Semiconductor device with capacitor arrangement electrically coupled to inductor coil
Publication Date: 2011.03.15 INFINEON TECHNOLOGIES AG
  • US7906831B2 patent drawing
  • US7906831B2 patent drawing
  • US7906831B2 patent drawing

AI summary

One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil.