Semiconductor Inductor with Insulator Slots for Quality Factor
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Solution Overview
Problem
Conventional inductor fabrication methods for RF applications below 1 GHz face challenges in achieving high quality factor while maintaining acceptable inductance and adhering to chemical-mechanical polishing (CMP) rules, as they often result in increased sidewall capacitance coupling and variability in the fabrication process.
Innovation Solution
The development of an inductor on a semiconductor substrate featuring a single or multiple metal layers with insulator slots embedded within, where the insulator slots are formed using silicon oxide and arranged along the coil, allowing for widening of the coil without violating CMP rules and enhancing the quality factor at sub-GHz frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal layers are stacked in parallel to achieve acceptable inductance and quality factor below 1 GHz, then the quality factor is improved, but sidewall capacitance coupling increases and broadband performance degrades
Solution Approach 1:
The patent extracts the harmful sidewall capacitance coupling effect by introducing insulator slots that remove the continuous metal-to-metal contact between stacked layers. The insulator slots create physical separation and insulation barriers that eliminate the parasitic capacitance paths while maintaining the inductive function of the stacked metal layers.
Solution Approach 2:
The patent introduces an intermediary insulator material (such as silicon oxide) filled in the slots between metal layers. This intermediary substance acts as a dielectric barrier that prevents direct electrical coupling between adjacent metal layers, thereby reducing sidewall capacitance while allowing the magnetic coupling necessary for inductance to persist.
2Reliability
If the coil of the inductor is widened to lower resistance and improve maximum quality factor, then the quality factor is improved, but CMP rules are violated and fabrication process variation increases
Solution Approach 1:
The patent applies local quality by selectively placing insulator slots at specific locations within the inductor structure where they provide maximum benefit. The slots are positioned to target areas with highest parasitic capacitance or resistance, allowing localized optimization without requiring global widening of the entire coil structure.
Solution Approach 2:
Instead of widening the coil in the lateral plane (which causes CMP and fabrication issues), the patent transitions to the vertical dimension by introducing insulator slots between stacked metal layers. This dimensional shift allows performance improvement through vertical insulation rather than horizontal expansion, avoiding the associated manufacturing problems.
3Loss of energy
If the coil of the inductor is widened to lower resistance, then the resistance is reduced, but fabrication process variation is significantly accentuated
Solution Approach 1:
The patent segments the continuous metal layer into sections separated by insulator slots. This segmentation allows the inductor to achieve lower effective resistance through multiple parallel current paths while maintaining standard-width metal segments that are within CMP and fabrication process control limits, thereby avoiding the variability associated with wide single segments.
Data Source
AI summary
An inductor formed on a semiconductor substrate is provided in the present invention. The inductor comprises a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.