Semiconductor Inductor Pad Arrangement for Eddy Current Reduction
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Solution Overview
Problem
In larger semiconductor devices, such as LSIs, the increased number of pads required for mounting can lead to a larger chip size due to their arrangement outside the circuit forming region, causing the magnetic field of inductors to generate eddy currents in these pads, which lowers the magnetic field strength and Q value.
Innovation Solution
The pads are arranged within the circuit forming region beneath the inductor, ensuring they do not overlap with the inductor in a plan view, thereby preventing eddy currents and maintaining a compact chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads are arranged outside the circuit forming region to accommodate increased number of pads in larger semiconductor devices, then the number of pads can be increased, but the chip size increases
Solution Approach 1:
The invention transitions pad arrangement from a two-dimensional planar layout to a three-dimensional vertical stacking configuration. Pads are positioned both within the circuit forming region and above it in different vertical layers, effectively utilizing the vertical dimension to increase pad capacity without expanding chip footprint.
Solution Approach 2:
The invention nests pads within the circuit forming region by positioning them in different vertical layers. The first conductive pads are located within the circuit forming region while the second conductive pads are positioned above this region, creating a nested vertical arrangement that maximizes space utilization.
2Area of stationary object
If pads are arranged within the circuit forming region to reduce chip size, then chip size is reduced, but eddy currents are generated in pads by the inductor's magnetic field lowering Q value
Solution Approach 1:
The invention segments the pad structure into two distinct groups positioned at different vertical locations: first conductive pads within the circuit forming region and second conductive pads above this region. This segmentation allows selective positioning to avoid eddy current generation while maintaining compact chip size.
Solution Approach 2:
The invention introduces an intermediary vertical spacing between the inductor and the first conductive pads positioned within the circuit forming region. This vertical separation acts as a mediator that prevents direct magnetic coupling between the inductor and pads, thereby eliminating eddy current generation while allowing pads to occupy the circuit forming region.
3Area of stationary object
If pads are positioned above the inductor to maximize space utilization, then space efficiency is improved, but eddy currents are generated canceling the magnetic field strength
Solution Approach 1:
The invention applies local quality differentiation by positioning second conductive pads above the circuit forming region but specifically avoiding direct overlap with the inductor's magnetic field region. This localized spatial arrangement allows space-efficient pad placement while preserving the inductor's magnetic field strength in critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement allows for a sufficient number of pads without increasing the chip size, while preventing eddy currents that would otherwise weaken the magnetic field, thus maintaining the Q value and chip size efficiency.
Implementation Method 1
the magnetic field of an inductor 101 generates an eddy current in pads 102 located above the inductor
Implementation Method 2
the magnetic field of an inductor 101 generates an eddy current in pads 102 located above the inductor (hatched portions). Then, this eddy current generates a magnetic field of a polarity so as to cancel the above described magnetic field following Lenz's law
Data Source
AI summary
A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.