Semiconductor Device Parasitic Inductance Compensation Resistor
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Solution Overview
Problem
The influence of parasitic inductance in bonding wires on semiconductor devices is not sufficiently reduced in existing technologies, and wire-free packaging solutions are expensive and require advanced mounting techniques.
Innovation Solution
A semiconductor device configuration that includes a semiconductor chip with a signal processing circuit and pads, where resistors are strategically placed between pads and connected by specific bonding wires to minimize the impact of parasitic inductance, with ESD protection devices for surge voltage protection, and no short-circuiting between pads to optimize signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bonding wires are used to connect pads to terminals, then the device can be manufactured with conventional techniques, but the parasitic inductance of the bonding wire deteriorates signal processing performance
Solution Approach 1:
The patent introduces a resistor as an intermediary element connected between the first pad and the reference potential supply terminal. This resistor serves as a mediator that compensates for the parasitic inductance effect of the bonding wire by providing a controlled impedance path, thereby improving signal processing performance while maintaining the use of conventional bonding wire connection techniques
Solution Approach 2:
The patent changes the electrical parameters of the circuit by adding a resistor with specific resistance value between the first pad and reference potential supply terminal. This parameter modification alters the overall impedance characteristics of the signal path, compensating for the parasitic inductance and improving signal integrity without changing the physical bonding wire structure
2Reliability
If wire-free packaging is used to eliminate parasitic inductance, then signal processing performance improves, but the device becomes expensive and requires advanced mounting technology
Solution Approach 1:
The patent uses a simple, inexpensive resistor as a compensating element that can be easily integrated into the conventional packaging structure. This low-cost component provides the necessary electrical compensation for parasitic inductance effects, achieving improved signal performance without requiring expensive wire-free packaging or advanced mounting technologies
Solution Approach 2:
The patent segments the signal path into distinct functional sections: the bonding wire connection, the pad structure, and the added resistor compensation network. By separating the compensation function into a distinct segment (the resistor), the solution allows conventional bonding wire packaging to be used while still achieving improved signal processing performance
Data Source
AI summary
A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.