3D Inductor Routing Density in Semiconductor Packages

The patent applies dimensionality change by transitioning from planar 2D inductor structures to 3D vertical structures. The inductors are formed with multiple levels using different metal layers (first metal layer, second metal layer) and via connections, creating a three-dimensional configuration that increases the effective inductor area without increasing the planar footprint. This allows higher routing density in the horizontal plane while maintaining adequate inductor quality factor through vertical stacking.

The patent implements nesting by placing inductor structures within and between routing layers. The inductors are embedded in the redistribution layer structure, with some inductors formed in lower metal layers and others in upper metal layers, creating a nested arrangement where inductor elements are integrated within the interconnect hierarchy. This nesting approach maximizes space utilization and maintains both routing density and inductor performance.

The patent applies segmentation by dividing the redistribution layer into multiple discrete metal layers (first metal layer, second metal layer) with distinct routing functions. Each layer can be independently patterned and controlled, allowing standard lithographic processes to maintain adequate manufacturing precision for each individual layer while achieving overall high routing density through the stacked configuration. This segmentation avoids the need to shrink dimensions within a single layer to extreme limits.

The patent resolves manufacturing precision challenges by moving from 2D planar routing to 3D multi-layer routing. Instead of shrinking interconnection dimensions in a single plane, the design utilizes vertical stacking to increase routing capacity. Each layer maintains manufacturable dimensions with standard precision controls, while the cumulative effect of multiple layers achieves the required overall routing density.